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Towards the Limits of Cascaded Reversible (Quantum-Inspired) Circuits

  • Stéphane Burignat
  • Mariusz Olczak
  • Michał Klimczak
  • Alexis De Vos
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7165)

Abstract

Several prototypes and proofs of concept of reversible (quantum-inspired) digital circuits have been successfully realized these last years, proving that digital reversible dual-line pass-transistor technology may be used for reversible linear computations. In order for this new technology to be used in commercial applications, several questions have to be answerd first. In particular, the number of gates possibly cascaded, the maximum reachable frequency, the maximum acceptable delays and amplitude drops are the key issues discussed in this paper.

Keywords

Very Large Scale Integration CNOT Gate Command Signal CMOS Circuit Transmission Gate 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Landauer, R.: Irreversibility and heat generation in the computing process. IBM Journal of Research and Development 5(3), 183–191 (1961)MathSciNetzbMATHCrossRefGoogle Scholar
  2. 2.
    Von Neumann, J.: Theory of self-reproducing automata, p. 66ss. University of Illinois Press, Urbana (1966)Google Scholar
  3. 3.
    Markov, I.: An introduction to reversible circuits. In: Proceedings of the 12th International Workshop on Logic and Synthesis, Laguna Beach, pp. 318–319 (May 2003)Google Scholar
  4. 4.
    Wille, R., Drechsler, R.: BDD-based synthesis of reversible logic for large functions. In: Proceedings of the 46th Design Automation Conference, San Francisco, pp. 270–275 (July 2009)Google Scholar
  5. 5.
    Wille, R., Drechsler, R.: Towards a design flow for reversible logic, 184 pages. Springer, Heidelberg (2010) ISBN:978-90-481-9578-7zbMATHCrossRefGoogle Scholar
  6. 6.
    Van Rentergem, Y., De Vos, A.: Reversible full adders applying Fredkin gates. In: Proceedings of the 12th International Conference on MIXed DESign of Integrated Circuits and Systems (MIXDES), Kraków, pp. 179–184 (June 2005)Google Scholar
  7. 7.
    Bennett, C.H.: Logical reversibility of computation. IBM Journal of Research and Development 17(6), 525–532 (1973)zbMATHCrossRefGoogle Scholar
  8. 8.
    De Vos, A.: Reversible computing, 249 pages. Wiley-VCH (2010) ISBN:978-3-527-40992-1Google Scholar
  9. 9.
    Cuccaro, S., Draper, T., Moulton, D., Kutin, S.: A new quantum ripple-carry addition circuit. In: Proceedings of the 8th Workshop on Quantum Information Processing, Cambridge (June 2005); arXiv:quant-ph/0410184v1, 9 pages (2004)Google Scholar
  10. 10.
    Burignat, S., De Vos A.: Test of a majority-based reversible (quantum) 4 bits ripple-carry adder in adiabatic calculation. In: Proceedings of the 18th International Conference on MIXed DESign of Integrated Circuits and Systems (MIXDES), Gliwice, Poland, pp. 368–373 (2011)Google Scholar
  11. 11.
    Feynman, R.P.: Quantum mechanical computer. Optics News 11, 11–20 (1985)CrossRefGoogle Scholar
  12. 12.
    Fredkin, E., Toffoli, T.: Conservative logic. International Journal of Theoretical Physics 21, 219–253 (2004)MathSciNetCrossRefGoogle Scholar
  13. 13.
    Burignat, S., Thomsen, M.K., Klimczak, M., Olczak, M., De Vos, A.: Interfacing Reversible Pass-Transistor CMOS Chips with Conventional Restoring CMOS Circuits. In: De Vos, A., Wille, R. (eds.) RC 2011. LNCS, vol. 7165, pp. 113–123. Springer, Heidelberg (2012)Google Scholar
  14. 14.
    Oklobdžija, V.G., Maksimović, D., Lin, F.: Pass-transistor adiabatic logic using single power-clock supply. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 44(10), 842–846 (1997)CrossRefGoogle Scholar
  15. 15.
    Lim, J., Kim, D.-G., Chae, S.-I.: A 16-bit carry-lookahead adder using reversible energy recovery logic for ultra-low-energy systems. IEEE Journal of Solid-State Circuits 34(6), 898–903 (1999)CrossRefGoogle Scholar
  16. 16.
    Hang, G., Wu, X.: Improved structure for adiabatic CMOS circuits design. Microelectronics Journal 33, 403–407 (2002)CrossRefGoogle Scholar
  17. 17.
    Ziesler, C.H., Kim, J., Papaefthymiou, M.C.: Energy recovering ASIC design. In: Proceedings of the IEEE Computer Society Annual Symposium on VLSI, Tampa, pp. 133–138 (2003)Google Scholar
  18. 18.
    Alioto, M., Palumbo, G., Poli, M.: Evaluation of energy consumption in RC ladder circuits driven by a ramp input. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12(10), 1094–1107 (2004)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Stéphane Burignat
    • 1
  • Mariusz Olczak
    • 1
  • Michał Klimczak
    • 1
  • Alexis De Vos
    • 1
    • 2
  1. 1.Vakgroep Elektronica en InformatiesystemenUniversiteit GentGentBelgium
  2. 2.Imec v.z.w.LeuvenBelgium

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