Abstract
Multi-threshold CMOS is an increasingly popular circuit approach that enables high performance and low power operation. In this paper Reverse Body Bias (RBB) with high-Vth is used to reduce the leakage power in nanometer technology for the proposed array multiplier with CSA design. The results are carried out by H-Spice for 90nm and 65nm BSIM model files. MTCMOS circuits have shown good results than the conventional circuits.
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References
Shiue, W.-T., Chakrabarti, C.: Memory Exploration for Low Power, Embedded Systems. In: 36th ACM/IEEE Design Automation Conference, New Orleans, pp. 140–145 (June 1999)
Shiue, W.-T., Chakrabarti, C.: Low Power Scheduling with Resources Operating at Multiple Voltages. EEE Transactions on Circuit and Systems Part II: Analog and Digital Signal Processing  47(6), 536–543 (2000)
Chandrakasan, A.P., Sheng, S., Brodersen, R.W.: Low-power CMOS digital design. IEEE Journal of Solid-State Circuits 27(4), 473–484 (1992)
Devadas, S., Keutzer, K., White, J.: Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation. IEEE Transactions on Computer-Aided Design 11(3), 373–383 (1992)
Kao, J., Chandrakasan, A., Antoniadis, D.: Transistor Sizing Issues and Tool For Multi-Threshold CMOS Technology. In: ACM Proceedings, DAC 1997 (1997)
Douseki, T., Shigematsu, S., Yamada, J., Harada, M., Inokawa, H., Tsuchiya, T.: A 0.5-V MTCMOS/SIMOX Logic Gate. IEEE Journal of Solid-State Circuits 32(10) (1997)
Liu, W.: Techniques for Leakage Power Reduction in Nanoscale Circuits: A Survey. IMM Technical Report (4) (2007)
Gu, R.X., Elmasry, M.I.: Power Dissipation Analysis and Optimization of Deep Submicron CMOS Digital Circuits. IEEE Journal of Solid State Circuits 31(5), 707–713 (1996)
Mutoh, S., et al.: 1-V Power Supply High-speed Digital Circuit Technology with Multi-threshold Voltage CMOS. IEEE Journal of Solid State Circuits 30(8), 847–854 (1995)
Al Zahrani, A., Bailey, A., Fu, G., Di., J.: Glitch-Free Design for Multi-Threshold CMOS NCL Circuits. In: ACM Proceedings of GLIVLSI 2009, May 10-12 (2009)
Bekiaris, D., Economakos, G., Pekmestzi, K.: A Mixed Style Multiplier Architecture for Low Dynamic and Leakage Power Dissipation. In: IEEE Conference, pp. 258–261 (May 2010)
Wen, M.-C., Wang, S.-J., Lin, Y.-N.: Low-power parallel multiplier with column bypassing. Electronics Letters 41(10) (2005)
Kuo, K.-C., Chou, C.W.: Low Power and High Speed multiplier design with row bypassing and parallel architecture. Microelectronics Journal 41, 639–650 (2010)
Ravi, N., Subba Rao, T., Jayachandra Prasad, T.: Performance Evaluation of Bypassing Array Multiplier with Optimized Design. International Journal of Computer Applications (IJCA) 28(5), 1–5 (2011)
Agarwal, A., et al.: Leakage Power Analysis and Reduction: Models, Estimation and Tools. Proc. IEEE 152(3), 353–368 (2005)
KeshavarziI, A., et al.: Effectiveness of Reverse Body Bias for Leakage Control in Scaled Dual Vt CMOS ICs. In: Proceedings of Int. Symp. Low Power Electronics and Desining, ISLPED1998, SIGDA 2001, pp. 207–212. ACM, New York (1998)
Butzen, P.F.: Leakage Current Modeling in Submicrometer CMOS Complex Gates, Master thesis (September 2007)
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Nirlakalla, R., Boothuru, B.R., Thota, S.R., Rajasekhar Babu, M., Talari, J.P., Venkata Krishna, P. (2012). Designing of Power Optimized Bypassing Array Multiplier in Nanometer Technology. In: Krishna, P.V., Babu, M.R., Ariwa, E. (eds) Global Trends in Information Systems and Software Applications. ObCom 2011. Communications in Computer and Information Science, vol 270. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-29216-3_30
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DOI: https://doi.org/10.1007/978-3-642-29216-3_30
Publisher Name: Springer, Berlin, Heidelberg
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