Abstract
The Discrete Cosine Transform (DCT)-based image compression is widely used in today’s communication systems. Significant research devoted to this domain has demonstrated that the optical compression methods can offer a higher speed but suffer from bad image quality and a growing complexity. To meet the challenges of higher image quality and high speed processing, in this chapter, we present a joint system for DCT-based image compression by combining a VLSI architecture of the DCT algorithm and an efficient quantization technique. Our approach is, firstly, based on a new granularity method in order to take advantage of the adjacent pixel correlation of the input blocks and to improve the visual quality of the reconstructed image. Second, a new architecture based on the Canonical Signed Digit and a novel Common Subexpression Elimination technique is proposed to replace the constant multipliers. Finally, a reconfigurable quantization method is presented to effectively save the computational complexity. Experimental results obtained with a prototype based on FPGA implementation and comparisons with existing works corroborate the validity of the proposed optimizations in terms of power reduction, speed increase, silicon area saving and PSNR improvement.
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Jridi, M., Alfalou, A. (2012). Joint Optimization of Low-Power DCT Architecture and Efficient Quantization Technique for Embedded Image Compression. In: Ayala, J.L., Atienza Alonso, D., Reis, R. (eds) VLSI-SoC: Forward-Looking Trends in IC and Systems Design. VLSI-SoC 2010. IFIP Advances in Information and Communication Technology, vol 373. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-28566-0_7
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DOI: https://doi.org/10.1007/978-3-642-28566-0_7
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