Abstract
This paper addresses complexity issues at algorithmic and architectural level of digital baseband receiver ASIC design for the standards GSM/GPRS/EDGE, in order to reduce power consumption and die area as desired for cellular applications. To this end, the hardware implementation of a channel shortening pre-filter combined with a delayed decision-feedback sequence estimatorĀ (DFSE) for channel equalization is described. The digital receiver back-end including a flexible Viterbi decoder implementation is presented and hardware savings that can be achieved by using hard-decisions are discussed. Design trade-offs are highlighted to prove the efficiency of the implemented 2.5G multi-mode architecture. The ASIC in 0.13 Ī¼m CMOS technology occupies 1.0 mm2 and dissipates only 1.3 mW in fastest EDGE data transmission mode.
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Benkeser, C., Huang, Q. (2012). Design and Optimization of a Digital Baseband Receiver ASIC for GSM/EDGE. In: Ayala, J.L., Atienza Alonso, D., Reis, R. (eds) VLSI-SoC: Forward-Looking Trends in IC and Systems Design. VLSI-SoC 2010. IFIP Advances in Information and Communication Technology, vol 373. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-28566-0_5
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DOI: https://doi.org/10.1007/978-3-642-28566-0_5
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