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International Symposium on Applied Reconfigurable Computing

ARC 2012: Reconfigurable Computing: Architectures, Tools and Applications pp 102–113Cite as

A Run-Time Task Migration Scheme for an Adjustable Issue-Slots Multi-core Processor

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Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 7199))

Abstract

In this paper, we present a run-time task migration scheme for an adjustable/reconfigurable issue-slots very long instruction word (VLIW) multi-core processor. The processor has four 2-issue ρ-VEX VLIW cores that can be merged together to form larger issue-width cores. With a task migration scheme, a code running on a core can be shifted to a larger or a smaller issue-width core for increasing the performance or reducing the power consumption of the whole system, respectively. All the cores can be utilized in an efficient manner, as a core needed for a specific job can be freed at run-time by shifting its running code to another core. The task migration scheme is realized with the implementation of interrupts on the ρ-VEX cores. The design is implemented in a Xilinx Virtex-6 FPGA. With different benchmarks, we demonstrate that migrating a task running on a smaller issue-width core to a larger issue-width core at run-time results in a considerable performance gain (up to 3.6x). Similarly, gating off one, two, three, or four cores can reduce the dynamic power consumption of the whole system by 24%, 42%, 61%, or 81%, respectively.

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Author information

Authors and Affiliations

  1. Computer Engineering Laboratory, Delft University of Technology, Mekelweg 4, 2628 CD, Delft, The Netherlands

    Fakhar Anjam, Quan Kong, Roel Seedorf & Stephan Wong

Authors
  1. Fakhar Anjam
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  2. Quan Kong
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  3. Roel Seedorf
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  4. Stephan Wong
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Editor information

Editors and Affiliations

  1. Department of Electronic Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong, China

    Oliver C. S. Choy

  2. Department of Electronic Engineering, City University of Hong Kong, Kowloon Tong, Hong Kong, China

    Ray C. C. Cheung

  3. Department of ECE, Virginia Tech., 302 Whittemore Hall, 24061, Blacksburg, VA, USA

    Peter Athanas

  4. Tohoku University, 6-6-01 Aramaki Aza Aoba, Aobaku, 981-8579, Sendai, Miyagi, Japan

    Kentaro Sano

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© 2012 Springer-Verlag Berlin Heidelberg

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Anjam, F., Kong, Q., Seedorf, R., Wong, S. (2012). A Run-Time Task Migration Scheme for an Adjustable Issue-Slots Multi-core Processor. In: Choy, O.C.S., Cheung, R.C.C., Athanas, P., Sano, K. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2012. Lecture Notes in Computer Science, vol 7199. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-28365-9_9

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  • DOI: https://doi.org/10.1007/978-3-642-28365-9_9

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-28364-2

  • Online ISBN: 978-3-642-28365-9

  • eBook Packages: Computer ScienceComputer Science (R0)

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