Abstract
FPGA-based processor prototyping system can fast simulate processor behavior and enables longer time simulations to obtain useful evaluation information. In this paper we present ScalableCore system 3.3, which is an FPGA-based simulator of NoC-based tile architectures by employing multiple Xilinx Spartan-6 FPGAs. Two key techniques enable the system to achieve scalable speed of simulations by using corresponding amount of FPGAs to the target number of processor cores. We evaluated behavior of a processor consisting of 100 cores and a mesh NoC by using our developed system. The simulation speed is 129 times faster than the one of a software-based simulator running on a standard computer of Core i7 processor.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Cell broadband engine, http://cell.scei.co.jp/
Binkert, N.L., Dreslinski, R.G., Hsu, L.R., Lim, K.T., Saidi, A.G., Reinhardt, S.K.: The M5 Simulator: Modeling Networked Systems. IEEE Micro 26, 52–60 (2006)
Monchiero, M.: How to simulate 1000 cores. SIGARCH Comput. Archit. News 37, 10–19 (2009)
Pellauer, M., Adler, M., Kinsy, M., Parashar, A., Emer, J.: Hasim: Fpga-based high-detail multicore simulation using time-division multiplexing. In: 2011 IEEE 17th International Symposium on High Performance Computer Architecture (HPCA), pp. 406–417 (February 2011)
Pellauer, M., Vijayaraghavan, M., Adler, M., Arvind, Emer, J.: A-ports: an efficient abstraction for cycle-accurate performance models on fpgas. In: Proceedings of the 16th International ACM/SIGDA Symposium on Field Programmable Gate Arrays, FPGA 2008, pp. 87–96. ACM, New York (2008)
Raghav, S., Ruggiero, M., Atienza, D., Pinto, C., Marongiu, A., Benini, L.: Scalable instruction set simulator for thousand-core architectures running on gpgpus. In: 2010 International Conference on High Performance Computing and Simulation (HPCS), pp. 459–466 (2010)
Sano, S., Sano, M., Sato, S., Miyoshi, T., Kise, K.: Pattern-based systematic task mapping for many-core processors. In: 2010 First International Conference on Networking and Computing (ICNC), pp. 173–178 (November 2010)
Sonmez, N., Arcas, O., Sayilar, G., Unsal, O., Cristal, A., Hur, I., Singh, S., Valero, M.: From Plasma to BeeFarm: Design Experience of an FPGA-Based Multicore Prototype. In: Koch, A., Krishnamurthy, R., McAllister, J., Woods, R., El-Ghazawi, T. (eds.) ARC 2011. LNCS, vol. 6578, pp. 350–362. Springer, Heidelberg (2011)
Takamaeda-Yamazaki, S., Sasakawa, R., Sakaguchi, Y., Kise, K.: An FPGA-based scalable simulation accelerator for tile architectures. SIGARCH Comput. Archit. News 39, 38–43 (2011)
Tan, Z., Waterman, A., Avizienis, R., Lee, Y., Cook, H., Patterson, D., Asanović, K.: RAMP gold: an FPGA-based architecture simulator for multiprocessors. In: DAC 2010: Proceedings of the 47th Design Automation Conference, pp. 463–468. ACM, New York (2010)
Uehara, K., Sato, S., Miyoshi, T., Kise, K.: A Study of an Infrastructure for Research and Development of Many-Core Processors. In: Workshop on Ultra Performance and Dependable Acceleration Systems Held in Conjunction with PDCAT 2009, pp. 414–419 (2009)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2012 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Takamaeda-Yamazaki, S., Sano, S., Sakaguchi, Y., Fujieda, N., Kise, K. (2012). ScalableCore System: A Scalable Many-Core Simulator by Employing over 100 FPGAs. In: Choy, O.C.S., Cheung, R.C.C., Athanas, P., Sano, K. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2012. Lecture Notes in Computer Science, vol 7199. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-28365-9_12
Download citation
DOI: https://doi.org/10.1007/978-3-642-28365-9_12
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-28364-2
Online ISBN: 978-3-642-28365-9
eBook Packages: Computer ScienceComputer Science (R0)