Static Task Mapping for Tiled Chip Multiprocessors with Multiple Voltage Islands

  • Nikita Nikitin
  • Jordi Cortadella
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7179)


The complexity of large Chip Multiprocessors (CMP) makes design reuse a practical approach to reduce the manufacturing and design cost of high-performance systems. This paper proposes techniques for static task mapping onto general-purpose CMPs with multiple pre-defined voltage islands for power management. The CMPs are assumed to contain different classes of processing elements with multiple voltage/frequency execution modes to better cover a large range of applications. Task mapping is performed with awareness of both on-chip and off-chip memory traffic, and communication constraints such as the link and memory bandwidth. A novel mapping approach based on Extremal Optimization is proposed for large-scale CMPs. This new combinatorial optimization method has delivered very good results in quality and computational cost when compared to the classical simulated annealing.


Chip Multiprocessing Task Mapping Power Management Extremal Optimization 


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  1. 1.
    Pham, D., et al.: Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor. J. Solid-State Circuits 41 (2006)Google Scholar
  2. 2.
    Bell, S., et al.: Tile64 - processor: A 64-core SoC with mesh interconnect. In: Solid-State Circuits Conference (2008)Google Scholar
  3. 3.
    Vangal, S., et al.: An 80-tile 1.28Tflops network-on-chip in 65nm CMOS. In: Solid-State Circuits Conference (2007)Google Scholar
  4. 4.
    Marculescu, R., Ogras, U.Y., Peh, L.-S., Jerger, N.E., Hoskote, Y.: Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives. IEEE Trans. on Computer-Aided Design of Integrated Circuits 28 (2009)Google Scholar
  5. 5.
    Azimi, M., et al.: Integration Challenges and Tradeoffs for Tera-scale Architectures. Intel. Technology Journal (2007)Google Scholar
  6. 6.
    Balakrishnan, S., Rajwar, R., Upton, M., Lai, K.: The impact of performance asymmetry in emerging multicore architectures. In: International Symposium on Computer Architecture (2005)Google Scholar
  7. 7.
    Lackey, D., et al.: Managing power and performance for System-on-Chip designs using voltage islands. In: Int. Conf. Computer-Aided Design (2002)Google Scholar
  8. 8.
    Kim, W., Gupta, M.S., Wei, G.-Y., Brooks, D.: System level analysis of fast, per-core DVFS using on-chip switching regulators. In: International Symposium on High Performance Computer Architecture (2008)Google Scholar
  9. 9.
    Mak, W.-K., Chen, J.-W.: Voltage island generation under performance requirement for SoC designs. In: Asia and South Pacific Design Automation Conference (2007)Google Scholar
  10. 10.
    Ghosh, P., Sen, A.: Energy efficient mapping and voltage islanding for regular NoC under design constraints. J. High Perform. Syst. Archit. 2 (2010)Google Scholar
  11. 11.
    Xu, R., Melhem, R., Mosse, D.: Energy-aware scheduling for streaming applications on chip multiprocessors. In: Int. Symp. Real-Time Systems (2007)Google Scholar
  12. 12.
    Hung, W.-L., et al.: Temperature-aware voltage islands architecting in System-on-Chip design. In: Int. Conf. Computer Design (2005)Google Scholar
  13. 13.
    Varatkar, G., Marculescu, R.: Communication-aware task scheduling and voltage selection for total systems energy minimization. In: Int. Conf. Computer-Aided Design (2003)Google Scholar
  14. 14.
    Chen, G., Li, F., Son, S., Kandemir, M.: Application mapping for chip multiprocessors. In: Design Automation Conference (2008)Google Scholar
  15. 15.
    Dally, W., Towles, B.: Principles and Practices of Interconnection Networks (2003)Google Scholar
  16. 16.
    Boettcher, S., Percus, A.G.: Extremal optimization: Methods derived from co-evolution. In: Genetic and Evolutionary Computation Conf. (1999)Google Scholar
  17. 17.
    Nikitin, N., Cortadella, J.: Static task mapping for tiled chip multiprocessors with multiple voltage islands. Technical Report (2011),
  18. 18.
    Kirkpatrick, S., Gelatt, C.D., Vecchi, M.P.: Optimization by simulated annealing. Science 220 (1983)Google Scholar
  19. 19.
    De Falco, I., Della Cioppa, A., Maisto, D., Scafuri, U., Tarantino, E.: A multiobjective extremal optimization algorithm for efficient mapping in grids 58 (2009)Google Scholar
  20. 20.

Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Nikita Nikitin
    • 1
  • Jordi Cortadella
    • 1
  1. 1.Universitat Politècnica de CatalunyaBarcelonaSpain

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