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Scheduling Architecture–Supported Regions in Parallel Programs

  • Marek Tudruj
  • Łukasz Maśko
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7133)

Abstract

Current multicore system technology enables implementation of particular program functions like library operations, special functions generation, optimized data search etc. using dedicated computing units to increase overall program performance. A parallel system can be equipped with a set of such units to speed up execution of applications, which use such functionality. To properly model and schedule programs using such functions running on a dedicated hardware, a proper program representation must be introduced. The paper presents special scheduling algorithm for programs represented as graphs, based on a modified ETF heuristics. The algorithm is meant for a modular architecture composed of many CMP modules interconnected by a global data communication network. The assumed architecture of dedicated CMP modules enables personalized fully synchronous program execution, which uses communication on the fly to strongly reduce inter–core communication overheads.

Keywords

CMP architectures program execution control program scheduling data communication optimization 

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References

  1. 1.
    Owens, J.D., et al.: Research Challenges for On–Chip Interconnection Networks. IEEE MICRO, 96–108 (September-October 2007)Google Scholar
  2. 2.
    Kundu, S., Peh, L.S.: On–Chip Interconnects for Multicores. IEEE MICRO, 3–5 (September-October 2007)Google Scholar
  3. 3.
    Koch, K.: Roadrunner System Overview, Los Alamos National Laboratory, http://www.lanl.gov/orgs/hpc/roadrunner/rrinfo/RR%20webPDFs/RRSystemOversm.pdf
  4. 4.
    Lepère, R., Trystram, D., Woeginger, G.J.: Approximation Algorithms for Scheduling Malleable Tasks Under Precedence Constraints. In: Meyer auf der Heide, F. (ed.) ESA 2001. LNCS, vol. 2161, pp. 146–157. Springer, Heidelberg (2001)CrossRefGoogle Scholar
  5. 5.
    Milenkovic, A., Milutinovic, V.: Cache Injection: A Novel Technique for Tolerating Memory Latency in Bus-Based SMPs. In: Bode, A., Ludwig, T., Karl, W.C., Wismüller, R. (eds.) Euro-Par 2000. LNCS, vol. 1900, pp. 558–566. Springer, Heidelberg (2000)CrossRefGoogle Scholar
  6. 6.
    Tudruj, M., Maśko, Ł.: Dynamic SMP Clusters with Communication on the Fly in NoC Technology for Very Fine Grain Computations. In: 3rd Int. Symp. on Parallel and Distributed Computing, ISPDC 2004, Cork, pp. 97–104 (July 2004)Google Scholar
  7. 7.
    Tudruj, M., Maśko, Ł.: Towards Massively Parallel Computations Based on Dynamic SMP Clusters wih Communication on the Fly. In: Proceedings of the 4th International Symposium on Parallel and Distributed Computing, ISPDC 2005, Lille, France, July 4-6, pp. 155–162. IEEE CS Press (2005)Google Scholar
  8. 8.
    Tudruj, M., Maśko, Ł.: Fast Matrix Multiplication in Dynamic SMP Clusters with Communication on the Fly in Systems on Chip Technology. In: Proc. of PARELEC 2006, pp. 77–82 (September 2006)Google Scholar
  9. 9.
    Masko, Ł., Dutot, P.–F., Mounié, G., Trystram, D., Tudruj, M.: Scheduling Moldable Tasks for Dynamic SMP Clusters in SoC Technology. In: Wyrzykowski, R., Dongarra, J., Meyer, N., Waśniewski, J. (eds.) PPAM 2005. LNCS, vol. 3911, pp. 879–887. Springer, Heidelberg (2006)CrossRefGoogle Scholar
  10. 10.
    Masko, Ł., Tudruj, M.: Task Scheduling for SoC–Based Dynamic SMP Clusters with Communication on the Fly. In: 7–th Int. Symp. on Parallel and Distributed Computing, ISPDC 2008, pp. 99–106 (2008)Google Scholar
  11. 11.
    Hwang, J.–J., Chow, Y.–C., Anger, F.D., Lee, C.–Y.: Scheduling precedence graphs in systems with interprocessor communication times. SIAM Journal on Computing 18(2) (1989)Google Scholar
  12. 12.

Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Marek Tudruj
    • 1
    • 2
  • Łukasz Maśko
    • 1
  1. 1.Institute of Computer Science of the Polish Academy of SciencesWarsawPoland
  2. 2.Polish–Japanese Institute of Information TechnologyWarsawPoland

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