Abstract
A number of concurrent error detection (CED) techniques have been proposed to detect transient errors in various types of circuits and systems. The CED techniques for sequential circuits (FSMs) presented in the literature are mostly aimed at implementations based on gates and flip-flops. Recently, a few techniques for circuits implemented using FPGAs have been proposed. Some of these techniques assume that an FSM is implemented using embedded memory blocks. In this paper, we present and compare a number of CED schemes for a specific design of a sequential circuit that includes the address modifier, intended for implementation in an FPGA with embedded memory blocks. The proposed set of CED schemes offers the designer an opportunity to trade-off error detection efficiency with implementation costs (circuitry overhead). In particular, some of the proposed solutions make it possible to achieve a reasonable level of error detection at the expense of less than 15% of circuitry overhead.
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Borowik, G., Kraśniewski, A. (2012). Trading-Off Error Detection Efficiency with Implementation Cost for Sequential Circuits Implemented with FPGAs. In: Moreno-Díaz, R., Pichler, F., Quesada-Arencibia, A. (eds) Computer Aided Systems Theory – EUROCAST 2011. EUROCAST 2011. Lecture Notes in Computer Science, vol 6928. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-27579-1_42
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DOI: https://doi.org/10.1007/978-3-642-27579-1_42
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-27578-4
Online ISBN: 978-3-642-27579-1
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