Abstract
We survey the recent developments of scheduling and allocation techniques in high level synthesis. Technology driven High-Level Synthesis is a customized high-level synthesis tool to make an optimal hardware generation, it makes the present knowledgeable of the target Field Programmable Gate Array. We then describe the different techniques and applications of different scheduling and allocation concepts in high level synthesis. To maximize the benefits of HLS, this paper describes the scheduling and allocation algorithms using Technology Specific Library (TSL).
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References
Joseph, M., Bhat, N.B., Chandra Sekaran, K.: Technology driven High-Level Synthesis. In: International Conference on Advanced Computing and Communication - ADCOM 2007. IEEE, Indian Institute of Technology Guwahati, India (2007)
Harish Ram, D.S., Bhuvaneswari, M.C., Logesh, S.M.: A Novel Evolutionary Technique for Multi objective Power, Area and Delay Optimization in High Level Synthesis of Datapaths. In: ISVLSI 2011, pp. 290–295 (2011)
Lin, C.-C., Yoon, D.-H.: New Efficient High Level Synthesis Methodology for Low Power Design. In: International Conference on New Trends in Information and Service Science (2009)
Wu, F., Xu, N., Zheng, F., Mao, F.: Simultaneous Functional Units and Register Allocation Based Power Management for High-level Synthesis of Data-intensive Applications (2010)
McFarland, M.C., Parker, A.C., Campasona, R.: Tutorial on High-Level Synthesis. In: 25th ACM IEEE Design Automation Conference (1998)
Brown, S.D., Francis, R.J., Rose, J., Vranesic, Z.G.: Field Programmable Gate Arrays. Kluwer Academic Publishers (1992)
Gajski, D.D., Dutt, N.D., Wu, A., Lin, S.: High-Level Synthesis: Introduction to Chip and System Design. Kluwer Academic Publishers (1992)
Yang, T., Peng, Z.: An efficient algorithm to integrate scheduling and allocation high-level test synthesis. In: Proceedings of Design Automation Test Eur., vol. 81, pp. 74–81 (1998)
Sllame, A., Drabek, V.: An Efficient List-Based Scheduling Algorithm for High-Level Synthesis. In: Proceedings Euromicro Symposium on Digital System Design DSD 2002, pp. 316–323. IEEE Computer Society (2002)
Kountouris, A., Wolinski, C.: Efficient Scheduling of Conditional behaviors for High Level Synthesis. ACM Transactions on Design Automation of Electronic Systems 7(3), 380–412 (2002)
Heijligers, M.J.M., Clutmans, L.J.M., Jess, J.A.G.: High-Level Synthesis Scheduling and Allocation using Genetic Algorithms. In: Proceedings of Asia and Pacific Design Automation Conference, Chiba, Japan, pp. 61–66 (1995)
Cabodi, G., Nocco, S., Lazarescu, M., et al.: A Symbolic Approach for the Combined Solution of Scheduling and Allocation. In: Proceedings of ISSS 2002, Kyoto, Japan, pp. 237–242 (2002)
Sait Sadique, M., Ali, S., Benten, M.S.: Scheduling and Allocation in High Level Synthesis using Stochastic Techniques. Microelectronics Journal 7 27(8), 693–712 (1991)
Sankaran, H., Katkoori, S.: Simultaneous Scheduling, Allocation, Binding, Re Ordering, and Encoding for Crosstalk Pattern Minimization During High Level Synthesis. IEEE Transaction on Very Large Scale Integration (VLSI) Systems 19(2) (2011)
Burns, F., Shang, D., Koelmans, A., Yakovlev, A.: Scheduling and allocation using closeness tables. IEE Proceedings - Computers and Digital Techniques 151(5), 332–340 (2004)
Free Floating-Point Madness, http://www.hmc.edu/chips
Electronic Design Interchange Format, http://www.edif.org
FPGA, CPLD, and EPP Solutions, http://www.xilinx.com
Icarus Verilog Simulation and Synthesis Tool, http://www.icraus.com
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© 2012 ICST Institute for Computer Science, Social Informatics and Telecommunications Engineering
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Chinnadurai, M., Joseph, M. (2012). Recent Developments in Scheduling and Allocation of High Level Synthesis. In: Meghanathan, N., Chaki, N., Nagamalai, D. (eds) Advances in Computer Science and Information Technology. Computer Science and Information Technology. CCSIT 2012. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 86. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-27317-9_34
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DOI: https://doi.org/10.1007/978-3-642-27317-9_34
Publisher Name: Springer, Berlin, Heidelberg
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