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Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 142))

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Abstract

Solid State Drives organize NAND flash memory in m-way & n-channel structure in order to increase the read/write throughput and the capacity. In m-way & n-channel structure, the basic read/write unit is usually multiples of physical page size. However, the influence of the read/write unit size on the performance has not been sufficiently studied. In this work, we investigate the influence of the read/write unit size on the representative FTL schemes. The results through a trace-driven simulation show that the optimal point is in the middle of small unit and large unit. Too large read/write unit hurts the performance seriously because small sized write requests occupy a considerable portion in windows PC. Especially, the performance of the page mapping scheme steeply decreases by large clustered page when the utilization is high.

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© 2012 Springer-Verlag GmbH Berlin Heidelberg

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Shin, I. (2012). Flash Translation Layer for Solid State Drives. In: Zhang, Y. (eds) Future Communication, Computing, Control and Management. Lecture Notes in Electrical Engineering, vol 142. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-27314-8_58

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  • DOI: https://doi.org/10.1007/978-3-642-27314-8_58

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-27313-1

  • Online ISBN: 978-3-642-27314-8

  • eBook Packages: EngineeringEngineering (R0)

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