Abstract
This paper provides a detailed survey of optimization techniques available in high level synthesis. This survey contemplates on two parts. The first part deals with the applicability of optimization techniques available in high level language compiler into high level synthesis. The second part address the topics such as Area optimization, Resource optimization, Power optimization and Optimization issues pertaining to the notions value-grouping, value to register assignment, Transfer to wire assignment and wire to FU port assignment.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Lin, C.-C., Yoon, D.-H.: New Efficient High Level Synthesis Methodology for Low Power Design. In: International Conference on New Trends in Information and Service Science (2009)
Joseph, M., Bhat, N.B., Chandra Sekaran, K.: Right inference of Hardware in High-Level Synthesis. In: International Conference on Information Processing, ICIP 2007, Bangalore, India (2007)
Zhang, J., Zhang, Z., Zhou, S., et al.: Bit-level optimization for high level synthesis and FGPA-based acceleration. In: Proceedings of FPGA 2010, Monterey, USA (2010)
Molina, M.C., Ruiz Sautra, R., Mendias, J.M., Hermida, R.: Area Optimization of multi-cycle operators in high level synthesis. In: Dte Conference Proceedings (2007)
McFarland, M.C., Parker, A.C., Campasona, R.: Tutorial on High-Level Synthesis. In: 25th ACM/IEEE Design Automation Conference (1998)
Flottes, M.L., Hammad, D., Rouzeyre, B.: High Level Synthesis for easy Testability. In: Proceedings of the European Design and Test Conference, Paris, France, pp. 198–206 (1995)
Potkonjak, M., Rabaey, J.: Optimizing Resource Utilization using Transformation. IEEE Trans. Computer Aided Design Integrated Circuits Systems 13(3), 227–292 (1994)
Lin, Y.L.: Recent Developments in High-Level Synthesis. ACM Transactions on Design Automation of Electronic Systems 2(1), 2–21 (1997)
Rabaey, J., Guerra, L., Mehra, R.: Design guidance in the power dimension. In: International Conference on Acoustics, Speech and Signal Processing, pp. 2837–2840 (1995)
Roy, S., Banerjee, P.: An Algorithm for Converting Floating-Point Computations to Fixed-Point in MATLAB based FPGA design. In: Design Automation Conference - DAC 2004, San Diego, California, pp. 484–487 (2004)
Raghunathan, A., Jha, N.K.: Behavioral Synthesis for low power. In: Proceedings of the International Conference on Computer Design (ICCD), pp. 318–322 (1994)
Neilson, S.G.: Behavioral synthesis of asynchronous circuits. PhD dessertation Technical University of Denmark, Department of Informatics and Mathematics modelling (2005)
Musoli, E., Cortadella, J.: Scheduling and Resource binding for low power. In: Proceedings of the Eighth Symposium on System Synthesis, pp. 104–109 (1995)
Ozer, E., Nisbet, A., Gregg, D.: Classification of Compiler Optimizations for High Performance. Small Area and Low Power in FPGAs (2003)
Joseph, M., Bhat, N.B., Chandra Sekaran, K.: Technology driven High-Level Synthesis. In: International Conference on Advanced Computing and Communication-ADCOM 2007. IEEE, Indian Institute of Technology, Guwahati, India (2007)
Taylor, S., Edwards, D., Plana, L.: Automatic compilation of data driven circuits. In: 14th IEEE International Symposium on Asynchronous Circuits and Systems, pp. 3–14. IEEE (2008)
Pasko, P., Schaumont, P., Derudder, V., Vernalde, S., Durackova, D.: A New algorithm for Elimination of Common Sub Expressions. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 18(1) (1999)
Muchnick, S.S.: Advanced Compiler Design Implementations. Harcourt Asia PTE Ltd. (1997)
Andres, E., Molina, M.C.: Area Optimization of Combined Integer and Floating Point Circuits in High Level Synthesis. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 8(1) (2008)
Liu, D., Svensson, C.: Power Consumption Estimation in CMOS VLSI Chips. IEEE Journal of Solid State Circuits 29(6) (1994)
Coog, J., Liu, B., Xu, J., et al.: Coordinated Resource Optimization in Behavioural Synthesis 20(2) (2009)
Katkoori, H.L., Liu, S.Z.: Feedback driven High Level Synthesis for performance optimization. In: ASICON 2005, 6th International Conference ASIC Proceedings, pp. 961–964 (2006)
Martin, R.S., Knight, J.P.: Power-profiler: Optimizing ASICs power consumption at the behavioral level. In: Proceedings of the Design Automation Conference (DAC), San Francisco, CA, p. 4247 (1995)
Free Floating-Point Madness, http://www.hmc.edu/chips
Electronic Design Interchange Format, http://www.edif.org
FPGA, CPLD, and EPP Solutions, http://www.xilinx.com
Icarus Verilog Simulation and Synthesis Tool, http://www.icraus.com
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2012 ICST Institute for Computer Science, Social Informatics and Telecommunications Engineering
About this paper
Cite this paper
Saravanakumaran, B., Joseph, M. (2012). Survey on Optimization Techniques in High Level Synthesis. In: Meghanathan, N., Chaki, N., Nagamalai, D. (eds) Advances in Computer Science and Information Technology. Computer Science and Engineering. CCSIT 2012. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 85. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-27308-7_2
Download citation
DOI: https://doi.org/10.1007/978-3-642-27308-7_2
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-27307-0
Online ISBN: 978-3-642-27308-7
eBook Packages: Computer ScienceComputer Science (R0)