Abstract
The paper presents two types of asynchronous comparators, i.e. asynchronous ripple comparator and pre-end asynchronous comparator. Compared to synchronous comparator, the asynchronous ripple comparator reduces power as it doesn’t have to compare all bits of data. However, asynchronous ripple comparators still need to deliver the comparison results bit by bit. The power consumption of the comparator also increases as the number of bits increase. The other type is pre-end asynchronous comparators. This type of comparators improves the truth table of comparison operation to control the computation of every bit. Only when the higher bits are equal can the next lower bit be computed so that power consumption is significantly reduced. At the end of the paper, comparisons between power consumption by 5-bit, 8-bit, 16-bit and 32-bit synchronous comparators and synchronous comparators are made. Among them, the power consumed by 32-bit asynchronous comparator is only 20.0% as much as that by synchronous comparators.
Grant from China National Natural Science Foundation fund: 60976031; grant from Basic Research Fund of South China University of Technology: 2009ZM0310; grant from fund of Science and Technology Department of Guangdong Province: 2009B080701060, 2010A080402015.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Chang, N., Henkel, J.: Curret trends in low power design. ACM Transactions on Design Automation of Electronic Systems 16(1) (November 2010)
Jiang, X., Nie, Z.-H.: Low Computational Complexity Algorithms of LDPC Decoder for CMMB. Acta Electronica Sinica (July 2010)
Huang, C.-H., Wang, J.-S.: High-performance and power-efficient CMOS comparators. Solid-State Circuits 38(2), 254–262 (2003)
Cheng, S.-W.: A high-speed magnitude comparator with small transistor count. Electronics, Circuits and Systems 3, 1168–1171 (2003)
Kim, J.-Y., Yoo, H.-J.: Bitwise Competition Logic for compact digital comparator. In: The 2007 IEEE Solid-State Circuits Conference, November 12-14, pp. 59–62. IEEE, Asian (2007)
Huang, C.-H., Wang, J.-S.: High-performance and power-efficient CMOS comparators. Solid-State Circuits 38(2), 254–262 (2003)
Kim, M., Kim, J.-Y., Yoo, H.-J.: A 1.55ns 0.015 mm2 64-bit quad number comparator. In: International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2009, pp. 283–286 (2009)
Zhao, B., Hei, Y., Qiu, Y.: A Performance Analysis Method of Asynchronous Data-path. Research & Progress of Solid State Electronics 24(3), 327–330 (2004)
Johnson, D., Akella, V.: Design and analysis of asynchronous adders. IEEE Proceedings Computers and Digital Techniques 145(1), 1–8 (1998)
Liu, Y.J, Steve, F.: The Design of an Asynchronous Carry-Lookahead Adder Based on Data Characteristics
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2011 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Jiang, X., Li, F. (2011). A New Design of Low Power Asynchronous Comparator. In: Zheng, D. (eds) Advances in Electrical Engineering and Electrical Machines. Lecture Notes in Electrical Engineering, vol 134. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-25905-0_41
Download citation
DOI: https://doi.org/10.1007/978-3-642-25905-0_41
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-25904-3
Online ISBN: 978-3-642-25905-0
eBook Packages: EngineeringEngineering (R0)