Abstract
Reed-Solomon (RS) codes play an important role in providing error protection and data integrity. Design of a scalable RS decoder is implemented with Bit-Parallel Systolic Multiplier. This bit-parallel multiplier is defined from All-One Polynomial. This can perform higher data throughput rate with shorter latency. As compared to other decoder architecture design the proposed work consist of less arithmetic operations and gate count is also comparably less.
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Gosavi, S.K., Ghodeswar, U.S., Sarate, G.G. (2011). Reed-Solomon Decoder Architecture Using Bit-Parallel Systolic Multiplier. In: Das, V.V., Thankachan, N. (eds) Computational Intelligence and Information Technology. CIIT 2011. Communications in Computer and Information Science, vol 250. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-25734-6_19
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DOI: https://doi.org/10.1007/978-3-642-25734-6_19
Publisher Name: Springer, Berlin, Heidelberg
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