Ultra Low Power 50 nm SRAM for Temperature Invariant Data Retention
Power efficient SRAM cell with temperature invariant data retention is very vital component in the design of deep-submicron Static memories. A novel ultra low power stable 8T-SRAM cell for 50 nm CMOS technology is analyzed for data retention property in this paper. It exhibits power reduction both in active mode and standby modes of operation and ideal data retention at operating temperature range of -500C to 1500C. Two additional NMOS transistors, one each in the pull down path the two inverters of standard 6-T SRAM cell utilize self correcting feedback to provide this performance. During the active mode one of the inverters (OFF) utilizes stack effect and the other inverter (ON) uses cascode amplification property to reduce power dissipation. Sub threshold leakage power is reduced by utilizing stack effect in the idle mode. Simulations using BSIM 4 models for 50nm technology and supply voltage value of 0.5V, indicate about 23X power savings in active mode and 28 X times in stand-by(data-retention) mode at 500C. The logic 1 data of the SRAM cell is retained at 499.74 mV for VDD of 500mV during standby (data retention) mode.
Keywordssubthreshold leakage power stack effect active mode power data retention cascode amplification static random-access memory (SRAM)
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