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Lightweight Implementations of SHA-3 Candidates on FPGAs

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Part of the book series: Lecture Notes in Computer Science ((LNSC,volume 7107))

Abstract

The NIST competition for developing the new cryptographic hash algorithm SHA-3 has entered its third round. One evaluation criterion is the ability of the candidate algorithm to be implemented on resource-constrained platforms. This includes FPGAs for embedded and hand-held devices. However, there has not been a comprehensive set of lightweight implementations for FPGAs reported to date. We hope to fill this gap with this paper in which we present lightweight implementations of all SHA-3 finalists and all round-2 candidates with the exception of SIMD. All implementations were designed to achieve maximum throughput while adhering to an area constraint of 400-600 slices and one Block RAM on Xilinx Spartan-3 devices. We also synthesized them for Virtex-V, Altera Cyclone-II, and the new Xilinx Spartan-6 devices.

This work has been supported in part by NIST through the Recovery Act Measurement Science and Engineering Research Grant Program, under contract no. 60NANB10D004.

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References

  1. ATHENa results database. Automated Tool for Hardware EvaluatioN project, http://cryptography.gmu.edu/athenadb/

  2. The SHA-3 Zoo. ECRYPT, Information Societies Technology (IST) Programme of the European Commission, http://ehash.iaik.tugraz.at/wiki/The_SHA-3_Zoo

  3. Announcing request for candidate algorithm nominations for a new cryptographic hash algorithm (SHA-3) family. Federal Register 72(212), notices 62212 (November 2007)

    Google Scholar 

  4. Aumasson, J.P., Henzen, L., Meier, W., Phan, R.C.W.: SHA-3 proposal BLAKE. Submission to NIST (Round 3) (2010), http://131002.net/blake/blake.pdf

  5. Baldwin, B., Hanley, N., Hamilton, M., Lu, L., Byrne, A., O’Neill, M., Marnane, W.P.: FPGA implementations of the round two SHA-3 candidates. Tech. rep., Second SHA-3 Candidate Conference (2010)

    Google Scholar 

  6. Benadjila, R., Billet, O., Gilbert, H., Macario-Rat, G., Peyrin, T., Robshaw, M., Seurin, Y.: SHA-3 proposal: ECHO. Submission to NIST (updated) (February 2009), http://crypto.rd.francetelecom.com/echo/

  7. Bernstein, D.J.: CubeHash specification (2.b.1). Submission to NIST (Round 2) (2009), http://cubehash.cr.yp.to/

  8. Bertoni, G., Daemen, J., Peeters, M., Gilles, V.A.: Keccak function version 2.0 (September 2009)

    Google Scholar 

  9. Bertoni, G., Daemen, J., Peeters, M., Van Assche, G.: Keccak sponge function family main document. version 1.2 (April 2009), http://keccak.noekeon.org

  10. Bertoni, G., Daemen, J., Peeters, M., Van Assche, G.: The Keccak SHA-3 submission. Submission to NIST (Round 3) (2011), http://keccak.noekeon.org/Keccak-submission-3.pdf

  11. Beuchat, J.L., Okamoto, E., Yamazaki, T.: Compact implementations of BLAKE-32 and BLAKE-64 on FPGA. Cryptology ePrint Archive, Report 2010/173 (2010)

    Google Scholar 

  12. Biham, E., Dunkelman, O.: The SHAvite-3 hash function. Submission to NIST (Round 2) (2009), http://www.cs.technion.ac.il/~orrd/SHAvite-3/Spec.15.09.09.pdf

  13. Bresson, E., et al.: Shabal, a submission to NISTs cryptographic hash algorithm competition. Submission to NIST (October 2008), http://ehash.iaik.tugraz.at/uploads/6/6c/Shabal.pdf

  14. Chen, Z., Morozov, S., Schaumont, P.: A hardware interface for hashing algorithms. Cryptology ePrint Archive, Report 2008/529 (2008), http://eprint.iacr.org/

  15. Cryptographic Engineering Research Group, George Mason University: Hardware Interface of a Secure Hash Algorithm (SHA), v. 1.4 edn. (January 2010)

    Google Scholar 

  16. De Cannière, C., Sato, H., Watanabe, D.: Hash function Luffa: Specification. Submission to NIST (Round 2) (October 2009), http://www.sdl.hitachi.co.jp/crypto/luffa/Luffa_v2_Specification_20091002.pdf

  17. Detrey, J., Gaudry, P., Khalfallah, K.: A low-area yet performant FPGA implementation of Shabal. Cryptology ePrint Archive, Report 2010/292 (2010)

    Google Scholar 

  18. Ferguson, N., Lucks, S., Schneier, B., Whiting, D., Bellare, M., Kohno, T., Callas, J., Walker, J.: The Skein hash function family. Submission to NIST (Round 3) (2010), http://www.skein-hash.info/sites/default/files/skein1.3.pdf

  19. Gaj, K., Chodowiec, P.: FPGA and ASIC Implementations of AES. In: Cryptographic Engineering, pp. 235–294. Springer, Heidelberg (2009)

    Chapter  Google Scholar 

  20. Gaj, K., Homsirikamol, E., Rogawski, M.: Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round two SHA-3 Candidates Using FPGA. In: Mangard, S., Standaert, F.-X. (eds.) CHES 2010. LNCS, vol. 6225, pp. 264–278. Springer, Heidelberg (2010)

    Chapter  Google Scholar 

  21. Gaj, K., Kaps, J.P., Amirineni, V., Rogawski, M., Homsirikamol, E., Brewster, B.Y.: ATHENa – Automated Tool for Hardware EvaluatioN: Toward fair and comprehensive benchmarking of cryptographic hardware using FPGAs. In: FPL 2010, pp. 414–421. IEEE (2010)

    Google Scholar 

  22. García-Vargas, I., Senhadji-Navarro, R., Jiménez-Moreno, G., Civit-Balcells, A., Guerra-Gutiérrez, P.: ROM-based finite state machine implementation in low cost FPGAs. In: Int. Symposium on Industrial Electronics, ISIE 2007, pp. 2342–2347. IEEE Press (June 2007)

    Google Scholar 

  23. Gauravaram, P., Knudsen, L.R., Matusiewicz, K., Mendel, F., Rechberger, C., Schäffer, M., Thomsen, S.S.: Grøstl – a SHA-3 candidate. Submission to NIST (October 2008), http://www.groestl.info/

  24. Gauravaram, P., Knudsen, L.R., Matusiewicz, K., Mendel, F., Rechberger, C., Schäffer, M., Thomsen, S.S.: Grøstl – a SHA-3 candidate. Submission to NIST (Round 3) (2011), http://www.groestl.info/Groestl.pdf

  25. Gligoroski, D., Klima, V., Knapskog, S.J., El-Hadedy, M., Amundsen, J., Mjølsnes, S.F.: Cryptographic hash function Blue Midnight Wish. Submission to NIST (Round 2) (September 2009), http://people.item.ntnu.no/~danilog/Hash/BMW-SecondRound/Supporting_Documentation/BlueMidnightWishDocumentation.pdf

  26. Halevi, S., Hall, W.E., Jutla, C.S.: The hash function Fugue. Submission to NIST (updated) (September 2009), http://domino.research.ibm.com/comm/research_projects.nsf/pages/fugue.index.html

  27. Homsirikamol, E., Rogawski, M., Gaj, K.: Comparing hardware performance of fourteen round two SHA-3 candidates using FPGAs. Cryptology ePrint Archive, Report 2010/445 (2010), http://eprint.iacr.org/

  28. Homsirikamol, E., Rogawski, M., Gaj, K.: Throughput vs. Area Trade-Offs Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs. In: Preneel, B., Takagi, T. (eds.) CHES 2011. LNCS, vol. 6917, pp. 491–506. Springer, Heidelberg (2011)

    Chapter  Google Scholar 

  29. Jungk, B.: Compact implementations of Grøstl, JH and Skein for FPGAs. In: ECRYPT II Hash Workshop 2011 (May 2011)

    Google Scholar 

  30. Jungk, B., Reith, S.: On FPGA-based implementations of Grøstl. Cryptology ePrint Archive, Report 2010/260 (2010)

    Google Scholar 

  31. Kerckhof, S., Durvaux, F., Veyrat-Charvillon, N., Regazzoni, F., de Dormale, G.M., Standaert, F.X.: Compact FPGA implementations of the five SHA-3 finalists. In: ECRYPT II Hash Workshop 2011 (May 2011)

    Google Scholar 

  32. Kobayashi, K., Ikegami, J., Matsuo, S., Sakiyama, K., Ohta, K.: Evaluation of hardware performance for the SHA-3 candidates using SASEBO-GII. (January 2010), http://eprint.iacr.org/2010/010

  33. Küçük, Ö.: The hash function Hamsi. Submission to NIST (updated) (2009), http://www.cosic.esat.kuleuven.be/publications/article-1203.pdf

  34. Matsuo, S., Knežević, M., Schaumont, P., Verbauwhede, I., Satoh, A., Sakiyama, K., Ota, K.: How can we conduct “fair and consistent” hardware evaluation for SHA-3 candidate? Tech. rep., Second SHA-3 Candidate Conference (2010)

    Google Scholar 

  35. Namin, A., Hasan, M.: Hardware implementation of the compression function for selected SHA-3 candidates. Tech. Rep. 28, Centre for Applied Cryptographic Research (CACR), University of Waterloo (July 2009)

    Google Scholar 

  36. Namin, A., Hasan, M.: Implementation of the compression function for selected SHA-3 candidates on FPGA. In: International Parallel Distributed Processing Symposium, Workshops and Phd Forum (IPDPSW), pp. 1–4. IEEE (2010)

    Google Scholar 

  37. Rawski, M., Selvaraj, H., Luba, T.: An application of functional decomposition in ROM-based FSM implementation in FPGA devices. J. Syst. Archit. 51(6-7), 424–434 (2005)

    Article  Google Scholar 

  38. Research Centre for Information Security (RCIS), National Institute of Advanced Industrial Science and Technology (AIST): Side-channel Attack Standard Evaluation Board SASEBO-GII Specification, version 1.01 edn. (November 2009)

    Google Scholar 

  39. Sklyarov, V.: Synthesis and Implementation of RAM-Based Finite State Machines in fPGAs. In: Grünbacher, H., Hartenstein, R.W. (eds.) FPL 2000. LNCS, vol. 1896, pp. 718–728. Springer, Heidelberg (2000)

    Chapter  Google Scholar 

  40. Sönmez Turan, M., Perlner, R., Bassham, L.E., Burr, W., Chang, D., jen Chang, S., Dworkin, M.J., Kelsey, J.M., Paul, S., Peralta, R.: Status report on the second round of the SHA-3 cryptographic hash algorithm competition. In: NIST Interagency Report 7764, NIST, Gaithersburg (2011)

    Google Scholar 

  41. Tuan, T., Kao, S., Rahman, A., Das, S., Trimberger, S.: A 90nm low-power FPGA for battery-powered applications. In: FPGA 2006, ACM/SIGDA, pp. 3–11. ACM, New York (2006)

    Google Scholar 

  42. Wu, H.: The hash function JH. Submission to NIST (updated) (September 2009), http://icsd.i2r.a-star.edu.sg/staff/hongjun/jh/

  43. Wu, H.: The hash function JH. Submission to NIST (round 3) (2011), http://www3.ntu.edu.sg/home/wuhj/research/jh/jh_round3.pdf

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Kaps, JP. et al. (2011). Lightweight Implementations of SHA-3 Candidates on FPGAs. In: Bernstein, D.J., Chatterjee, S. (eds) Progress in Cryptology – INDOCRYPT 2011. INDOCRYPT 2011. Lecture Notes in Computer Science, vol 7107. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-25578-6_20

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  • DOI: https://doi.org/10.1007/978-3-642-25578-6_20

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-25577-9

  • Online ISBN: 978-3-642-25578-6

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