Abstract
Application Specific Instruction Set Processors (ASIPs) have become popular in the development of embedded systems. For these processors easily-retargetable, high-performance compilers play a key role in the development process, improving productivity and reducing time-to-market. We propose a novel, object-based architecture description language (ADL) OpenDL, as well as a well-structured Rule Library to automatically retarget compiler backends. OpenDL is a succinct and high-quality ADL with object-based inheritance features, while the Rule Library applies instruction templating in order to allow detailed instruction specification to handle complex rule patterns. We use these tools to automatically retarget the open source industrial-strength compiler Open64 to the high-performance embedded processor PowerPC. A reliable version of auto-retargetable industrial-strength compiler is generated which achieves comparable performance to gcc 4.5 for both the EEMBC and SPEC CPU 2000 benchmarks.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Aho, A.V., Ganapathi, M., Tjiang, S.W.K.: Code generation using tree matching and dynamic programming. ACM Transactions on Programming Languages and Systems 11(4), 491–516 (1989)
Azevedo, R., Rigo, S., Bartholomeu, M., Araujo, G., Araujo, C., Barros, E.: The archc architecture description language and tools. International Journal of Parallel Programming 33(5), 453–484 (2005)
Bashford, S., Bieker, U., Harking, B., Leupers, R., Marwedel, P., Neumann, A., Voggenauer, D.: The mimola language, version 4.1. University of Dortmund (September 1994)
Brandner, F., Ebner, D., Krall, A.: Compiler generation from structural architecture descriptions. In: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, pp. 13–22 (October 2007)
Ceng, J., Sheng, W., Hohenauer, M., Leupers, R., Ascheid, G., Meyr, H.: Modeling instruction semantics in ADL processor descriptions for C compiler retargeting. Journal of VLSI Signal Processing 43, 235–246 (2006)
Cui, H., Feng, X.: Retargeting open64 to a RISC processor – a students perspective. In: Open64 Workshop at CGO (2008)
De, S.K., Dasgupta, A., Kushwaha, S., Linthicum, T., Brownhill, S., Larin, S., Simpson, T.: Development of an efficient DSP compiler based on open64. In: Open64 Workshop at CGO (2008)
Fraser, C.W., Hanson, D., Proebsting, T.A.: Engineering a simple, efficient code generator generator. ACM Letters on Programming Languages and Systems 1(3), 213–226 (1992)
Fraser, C.W., Henry, R.R., Proebsting, T.A.: Burg: Fast optimal instruction selection and tree parsing. ACM SIGPLAN Notices 27(4), 68–76 (1992)
Freericks, M.: The nml machine description formalism, version 1.5. TU Berlin Computer Science Technical Report (1993)
George Hadjiyiannis, S.H., Devadas, S.: Isdl: An instruction set description language for retargetability. In: Design Automation Conference, pp. 299–302 (1997)
Graham, S.L.: Table-driven code generation. Computer 13(8), 25–34 (1980)
Group, S.R.: Spam compiler user’s manual (1997)
Gyllenhaal, J.C.: A machine description language for compilation. Master Thesis, Department of EE, UIUC (1994)
Halambi, A., Grun, P., Ganesh, V., Khare, A.: Expression: A language for architecture exploration through compiler/simulator retargetability. In: Design, Automation and Test in Europe, pp. 485–490 (1999)
Hanono, S., Devadas, S.: Instruction selection, resource allocation, and scheduling in the aviv retargetable code generator. In: Design Automation Conference, pp. 510–515 (1998)
Hohenauer, M., Engel, F., Leupers, R., Ascheid, G., Meyr, H., Bette, G., Singh, B.: Retargetable code optimization for predicated execution. In: Design, Automation and Test in Europe, pp. 1492–1497 (2008)
Hohenauer, M., Scharwaechter, H., Karuri, K., Wahlen, O., Kogel, T., Leupers, R., Ascheid, G., Meyr, H., Braun, G., van Someren, H.: A methodology and tool suite for C compiler generation from ADL processor models. In: Design, Automation and Test in Europe, vol. 2, pp. 21–26 (2004)
Lanneer, D., Praet, J.V., Kifli, A., Schoofs, K., Geurts, W., Thoen, F., Goossens, G.: Chess: Retargetable code generation for embedded DSP processors. Code Generation for Embedded Processors, pp. 85–102 (1995)
Leupers, R., Marwedel, P.: Retargetable code generation based on structural processor descriptions. Design Automation for Embedded Systems 3(1), 75–108 (1998)
Lin, M., Yu, Z., Zhang, D., Zhu, Y., Wang, S., Dong, Y.: Retargeting the open64 compiler to powerpc processor. In: The 2008 International Conference on Embedded Software and Systems Symposia, pp. 152–157 (2008)
Liu, S.-M.: A tutorial: Open64 release 4.0: High performance compiler for itanium and x86 linux. In: PLDI (2007)
Lo, K.M., Ma, L.: Quantitative approach to ISA design and compilation for code size reduction. In: Open64 Workshop at CGO (2008)
Mishra, P., Shrivastava, A., Dutt, N.: Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable socs. ACM Transactions on Design Automation of Electronic Systems 11(3), 626–658 (2006)
Murphy, M.: Nvidia’s experience with open64. In: Open64 Workshop at CGO (2008)
Pees, S., Hoffmann, A., Zivojnovic, V., Meyr, H.: Lisa - machine description language for cycle-accurate models of programmable DSP architectures. In: Design Automation Conference, pp. 933–938 (1999)
Proebsting, T.A.: Simple and efficient burs table generation. In: PLDI, pp. 331–340 (1992)
Shuchang, Z., Ying, L., Fang, L., Le, Y., Lei, H., Shuai, L., Chunhui, M., Zhitao, G., Ruiqi, L.: Open64 on mips: porting and enhancing open64 for loongson ii. In: Open64 Workshop at CGO (2008)
Tensilica, http://www.tensilica.com
Trimaran: Trimaran: A compiler and simulator for research on embedded and epic architecture, version 4.0 (April 2007), http://www.trimaran.org/docs/trimaran4_manual.pdf
Wahlen, O., Hohenauer, M., Braun, G., Leupers, R., Ascheid, G., Meyr, H., Nie, X.: Extraction of Efficient Instruction Schedulers from Cycle-True Processor Models. In: Anshelevich, E. (ed.) SCOPES 2003. LNCS, vol. 2826, pp. 167–181. Springer, Heidelberg (2003)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2011 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Cao, Z., Dong, Y., Wang, S. (2011). Compiler Backend Generation for Application Specific Instruction Set Processors. In: Yang, H. (eds) Programming Languages and Systems. APLAS 2011. Lecture Notes in Computer Science, vol 7078. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-25318-8_12
Download citation
DOI: https://doi.org/10.1007/978-3-642-25318-8_12
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-25317-1
Online ISBN: 978-3-642-25318-8
eBook Packages: Computer ScienceComputer Science (R0)