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Many-Core Architecture Oriented Parallel Algorithm Design for Computer Animation

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Motion in Games (MIG 2011)

Part of the book series: Lecture Notes in Computer Science ((LNIP,volume 7060))

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Abstract

Many-core architecture has become an emerging and widely adopted platform for parallel computing. Computer animation researches can harness this advance in high performance computing with better understanding of the architecture and careful consideration of several important parallel algorithm design issues, such as computation-to-core mapping, load balancing and algorithm design paradigms. In this paper, we use a set of algorithms in computer animation as the examples to illustrate these issues, and provide possible solutions for handling them. We have shown in our previous research projects that the proposed solutions can greatly enhance the performance of the parallel algorithms.

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References

  1. AMD: Fusion family of apus, http://sites.amd.com/us/fusion/apu/Pages/fusion.aspx

  2. Arikan, O., Forsyth, D.A.: Interactive motion generation from examples. ACM Trans. Graph. 21(3), 483–490 (2002)

    Article  MATH  Google Scholar 

  3. Arikan, O., Forsyth, D.A., O’Brien, J.F.: Motion synthesis from annotations. In: ACM SIGGRAPH 2003 Papers, SIGGRAPH 2003, pp. 402–408. ACM, New York (2003), http://doi.acm.org/10.1145/1201775.882284

    Google Scholar 

  4. Bakkum, P., Skadron, K.: Accelerating sql database operations on a gpu with cuda. In: Proceedings of the 3rd Workshop on General-Purpose Computation on Graphics Processing Units, GPGPU 2010, pp. 94–103. ACM, New York (2010), http://doi.acm.org/10.1145/1735688.1735706

    Google Scholar 

  5. Cao, Y., Patnaik, D., Ponce, S., Archuleta, J., Butler, P., chun Feng, W., Ramakrishnan, N.: Towards chip-on-chip neuroscience: Fast mining of frequent episodes using graphics processors. Tech. rep., arXiv.org (2009)

    Google Scholar 

  6. Cao, Y., Patnaik, D., Ponce, S., Archuleta, J., Butler, P., chun Feng, W., Ramakrishnan, N.: Towards chip-on-chip neuroscience: Fast mining of neuronal spike streams using graphics hardware. In: CF 2010: Proceedings of the 7th ACM International Conference on Computing Frontiers, May 17 - 19, pp. 1–10, No. 978-1-4503-0044-5. ACM, Bertinoro (2010)

    Google Scholar 

  7. Cederman, D., Tsigas, P.: Gpu-quicksort: A practical quicksort algorithm for graphics processors. J. Exp. Algorithmics 14, 4:1.4–4:1.24 (2010), http://doi.acm.org/10.1145/1498698.1564500

    MATH  Google Scholar 

  8. Dean, J., Ghemawat, S.: Mapreduce: simplified data processing on large clusters. Commun. ACM 51, 107–113 (2008), http://doi.acm.org/10.1145/1327452.1327492

    Article  Google Scholar 

  9. Fang, W., He, B., Luo, Q., Govindaraju, N.K.: Mars: Accelerating mapreduce with graphics processors. IEEE Trans. Parallel Distrib. Syst. 22, 608–620 (2011), http://dx.doi.org/10.1109/TPDS.2010.158

    Article  Google Scholar 

  10. Hagan, R., Cao, Y.: Multi-gpu load balancing for in-situ visualization. In: The 2011 International Conference on Parallel and Distributed Processing Techniques and Applications (to appear in, 2011)

    Google Scholar 

  11. Huang, J., Ponce, S., Park, S.I., Cao, Y., Quek, F.: Gpu-accelerated computation for robust motion tracking using the cuda framework. In: VIE 2008 - The 5th IET Visual Information Engineering 2008 Conference, July 29 - August 1, pp. 437–442 (2008)

    Google Scholar 

  12. Intel: Sandy bridge architecture, http://www.intel.com/content/www/us/en/processors/core/core-i5-processor.html

  13. Lee, V.W., Kim, C., Chhugani, J., Deisher, M., Kim, D., Nguyen, A.D., Satish, N., Smelyanskiy, M., Chennupaty, S., Hammarlund, P., Singhal, R., Dubey, P.: Debunking the 100x gpu vs. cpu myth: an evaluation of throughput computing on cpu and gpu. In: Proceedings of the 37th Annual International Symposium on Computer Architecture, ISCA 2010, pp. 451–460. ACM, New York (2010), http://doi.acm.org/10.1145/1815961.1816021

    Google Scholar 

  14. Patnaik, D., Ponce, S.P., Cao, Y., Ramakrishnan, N.: Accelerator-oriented algorithm transformation for temporal data mining, pp. 93–100. IEEE Computer Society, Los Alamitos (2009)

    Google Scholar 

  15. Sengupta, S., Harris, M., Zhang, Y., Owens, J.D.: Scan primitives for gpu computing. In: Proceedings of the 22nd ACM SIGGRAPH/EUROGRAPHICS Symposium on Graphics Hardware, GH 2007, pp. 97–106. Eurographics Association, Aire-la-Ville (2007), http://dl.acm.org/citation.cfm?id=1280094.1280110

    Google Scholar 

  16. Stuart, J.A., Chen, C.K., Ma, K.L., Owens, J.D.: Multi-gpu volume rendering using mapreduce. In: Proceedings of the 19th ACM International Symposium on High Performance Distributed Computing, HPDC 2010, pp. 841–848. ACM, New York (2010), http://doi.acm.org/10.1145/1851476.1851597

    Google Scholar 

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Cao, Y. (2011). Many-Core Architecture Oriented Parallel Algorithm Design for Computer Animation. In: Allbeck, J.M., Faloutsos, P. (eds) Motion in Games. MIG 2011. Lecture Notes in Computer Science, vol 7060. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-25090-3_16

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  • DOI: https://doi.org/10.1007/978-3-642-25090-3_16

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-25089-7

  • Online ISBN: 978-3-642-25090-3

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