A VLSI Spiking Neural Network with Symmetric STDP and Associative Memory Operation

Abstract

This paper proposes an analog CMOS VLSI circuit which implements integrate-and-fire spiking neural networks with spike-timing dependent synaptic plasticity (STDP). The designed VLSI chip includes 25 neurons and 600 synapse circuits with symmetric all-to-all connection STDP. Using the fabricated VLSI chip, we implement a Hopfield-type feedback network, and demonstrate its associative memory operation. In our chip, analog information is represented by the relative timing of spike firing events. Symmetric STDP provides an auto-correlation learning function depending on relative timing between spikes consisting of a learning pattern. Each learning and test pattern consists of 20 spike pulses each of which has a relative delay corresponding to a gray-scale pixel intensity. The chip has successfully associated from an input pattern the most similar learning pattern.