On the Use of Multiplanes on a 2D Mesh Network-on-Chip

  • Cruz Izu
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7017)


Alike interconnection networks for parallel systems, Networks-on-chip (NoC) must provide high bandwidth and low latency, but they are further constrained by their on-chip power budget. Consequently, simple network topologies such as the 2D Mesh with shallow buffers and simple routing strategies such as dimensional order routing (DOR) have been widely used in order to achieve this goal. A low number of virtual channels could be used to eliminate head-of-line blocking and increase network throughput.

Due to the spare routing area in deep submicron technology, another possibility is to replicate the simple network once or more times. This work compares and combines the two approaches, by considering the distribution of a fixed number of virtual channels over one or more multiplanes. A thorough evaluation of the possible 2D mesh network configurations under a range of workloads will show that, provided there is spare area, replicating the 2D mesh with 2 virtual channels results on the best power/performance trade-off.


Network-on chip replication virtual channels evaluation 


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  1. 1.
    Balfour, J., Dally, W.J.: Design tradeoffs for tiled CMP on-chip networks. In: Proceedings of the 20th Annual International Conference on Supercomputing (ICS 2006), pp. 187–198. ACM, New York (2006), doi:10.1145/1183401.1183430CrossRefGoogle Scholar
  2. 2.
    Dally, W.J.: Virtual-Channel Flow Control. IEEE Trans. Parallel Distrib. Syst. 3(2), 194–205 (1992), doi:10.1109/71.127260CrossRefGoogle Scholar
  3. 3.
    Dally, W.J., Towles, B.: Route packets, not wires: on-chip interconnection networks. In: Proceedings of the 38th Annual Design Automation Conference (DAC 2001), pp. 684–689. ACM, New York (2001), doi:10.1145/378239.379048Google Scholar
  4. 4.
    Carara, E., Moraes, F., Calazans, N.: Router architecture for high-performance NoCs. In: Proceedings of the 20th Annual Conference on Integrated Circuits and Systems Design (SBCCI 2007), pp. 111–116. ACM, New York (2007), doi:10.1145/1284480.1284515CrossRefGoogle Scholar
  5. 5.
    Duato, J., Yalamanchili, S., Ni, L.: Interconnection Networks: an engineering Approach. IEEE Computer Society Press, Los Alamitos (1997)Google Scholar
  6. 6.
    Gilabert, F., Gomez, M.E., Medardoni, S., Bertozzi, D.: Improved Utilization of NoC Channel Bandwidth by Switch Replication for Cost-Effective Multi-processor Systems-on-Chip. In: Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip (NOCS 2010), pp. 165–172. IEEE Computer Society, Washington, DC, USA (2010),, doi:10.1109/NOCS.2010.25CrossRefGoogle Scholar
  7. 7.
    Gratz, P., Kim, C., Sankaralingam, K., Hanson, H., Shivakumar, P., Keckler, S.W., Burger, D.: On-Chip Interconnection Networks of the TRIPS Chip. IEEE Micro 27(5), 41–50 (2007), doi:10.1109/MM.2007.90CrossRefGoogle Scholar
  8. 8.
    Jesshope, C.R., Izu, C.: The MP1 Network Chip and its Application to Parallel Computers. The Computer Journal 36(8), 763–777 (1993), doi:10.1093/comjnl/36.8.763 CrossRefGoogle Scholar
  9. 9.
    Kahng, A., Li, B., Peh, L.-S., Samadi, K.: Orion 2.0: A fast and accurate noc power and area model for early-stage design space exploration. In: Proceedings of the Conference on Design, Automation and Test in Europe. ACM, New York (2009)Google Scholar
  10. 10.
    Matsutani, H., Koibuchi, M., Wang, D., Amano, H.: Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks. In: Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip (NOCS 2008), pp. 23–32. IEEE Computer Society, Washington, DC, USA (2008)CrossRefGoogle Scholar
  11. 11.
    Noh, S., Ngo, V.-D., Jao, H., Choi, H.-W.: Multiplane Virtual Channel Router for Network-on-Chip Design. In: First International Conference on Communications and Electronics, ICCE 2006, October 10-11, pp. 348–351 (2006), doi:10.1109/CCE.2006.350796 Google Scholar
  12. 12.
    Owens, J.D., Dally, W.J., Ho, R., Jayasimha, D.N., Keckler, S.W., Peh, L.-S.: Research Challenges for On-Chip Interconnection Networks. IEEE Micro 27(5), 96–108 (2007)CrossRefGoogle Scholar
  13. 13.
    Shang, L., Peh, L.-S., Jha, N.K.: Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks. In: Proceedings of the 9th IEEE International Symposium on High-Performance Computer Architecture, pp. 79–90 (February 2003)Google Scholar
  14. 14.
    Sankaralingam, K., Nagarajan, R., Gratz, P., Desikan, R., Gulati, D., Hanson, H., Kim, C., Liu, H., Ranganathan, N., Sethumadhavan, S., Sharif, S., Shivakumar, P., Yoder, W., McDonald, R., Keckler, S.W., Burger, D.C.: The Distributed Microarchitecture of the TRIPS Prototype Processor. In: 39th International Symposium on Microarchitecture (MICRO) (December 2006)Google Scholar
  15. 15.
    Vangal, S.R., et al.: An 80-tile sub-100w teraflops processor in 65-nm cmos. IEEE Journal of Solid-State Circuits (2008)Google Scholar
  16. 16.
    Yoon, Y.J., Concer, N., Petracca, M., Carloni, L.: Virtual channels vs. multiple physical networks: a comparative analysis. In: Proceedings of the 47th Design Automation Conference (DAC 2010), pp. 162–165. ACM, New York (2010), doi:10.1145/1837274.1837315Google Scholar

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© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Cruz Izu
    • 1
  1. 1.School of Computer ScienceThe University of AdelaideAdelaideSouth Australia

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