Equivalence Checking between Function Block Diagrams and C Programs Using HW-CBMC

  • Dong-Ah Lee
  • Junbeom Yoo
  • Jang-Soo Lee
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6894)


Controllers in safety critical systems such as nuclear power plants often use Function Block Diagrams (FBDs) to design embedded software. The design program are translated into programming languages such as C to compile it into machine code for particular target hardware. It is required to verify equivalence between the design and the implementation, because the implemented program should have same behavior with the design. This paper introduces a technique about verifying equivalence between a design written in FBDs and its implementation written in C language using HW-CBMC. To demonstrate the effectiveness of our proposal, as a case study, we used one of 18 shutdown logics in a prototype of Advanced Power Reactor’s (APR-1400) Reactor Protection System (RPS) in Korea. Our approach is effective to check equivalence between FBDs and ANSI-C programs if the automatically generated Verilog program is translated into appropreate one of the HW-CBMC.


Equivanelce Checking Behavioral Consistency FBDs Verilog ANSI-C HW-CBMC 


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  1. 1.
    Korea Nuclear Instrumentation & Control System R&D Conter,
  2. 2.
    Cho, S., Koo, K., You, B., Kim, T.-W., Shim, T., Lee, J.S.: Development of the loader software for PLC programming. In: Proceedings of Conference of the Institute of Electronics Engineerers of Korea, vol. 30(1), pp. 595–960 (2007)Google Scholar
  3. 3.
    Hoare, T.: The Verifying Compiler: A Grand Challenge for Computing Research. Journal of the ACM 50, 63–69 (2003)CrossRefzbMATHGoogle Scholar
  4. 4.
    RETRANS, Institue for Safety Technology (ISTec),
  5. 5.
    Clarke, E., Kroening, D.: Hardware verification using ANSI-C programs as a reference. In: Proceedings of the 2003 Asia and South Pacific Design Automation Conference, pp. 308–311 (2003)Google Scholar
  6. 6.
    Yoo, J., Cha, S., Jee, E.: Verification of PLC programs written in FBD with VIS. Nuclear Engineering and Technology 41(1), 79–90 (2009)CrossRefGoogle Scholar
  7. 7.
    IEEE: IEEE standard hardware dexcription language based on the Verilog hardware description language. (IEEE Std. 1364-2001) (2001)Google Scholar
  8. 8.
    Bombieri, N., Fummi, F., Pravadelli, G., Marques-Silva, J.: Towards Equivalence Checking Between TLM and RTL Models. In: 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign, MEMOCODE 2007, pp. 113–122 (2007)Google Scholar
  9. 9.
    Sangiovanni-Vincentelli, A., Aziz, A., Cheng, S.-T., Edwards, S., Khatri, S., Kukimoto, Y., Qadeer, S., Shiple, T.R., Swamy, G., Hachtel, G.D., Somenzi, F., Pardo, A., Ranjan, R.K., Brayton, R.K.: VIS: A System for Verification and Synthesis. In: Alur, R., Henzinger, T.A. (eds.) CAV 1996. LNCS, vol. 1102, pp. 428–432. Springer, Heidelberg (1996)CrossRefGoogle Scholar
  10. 10.
    McMillan, K.L.: Symbolic Model Checking. Kluwer Academic Publishers, Dordrecht (1993)CrossRefzbMATHGoogle Scholar
  11. 11.
    IEC (International standard for programmable controllers): Programming languages 61131- Part 3 (1993)Google Scholar
  12. 12.
    Jee, E., Jeon, S., Cha, S., Koh, K., Yoo, J., Park, G., Seong, P.: FBDVerifier: Interactive and Visual Analysis of Counterexample in Formal Verification of Function Block Diagram. Journal of Research and Practice in Information Technology 42(3), 255–272 (2010)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Dong-Ah Lee
    • 1
  • Junbeom Yoo
    • 1
  • Jang-Soo Lee
    • 2
  1. 1.Division of Computer Science and EngineeringKonkuk UniversitySeoulRepublic of Korea
  2. 2.Korea Atomic Energy Research InstituteDaejeonRepublic of Korea

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