Abstract
Contrary to the existing techniques to realize inexact circuits that relied mostly on scaling of supply voltage or pruning of “least-significant” components in conventional correct circuits to achieve cost (energy, delay and/or area) and accuracy tradeoffs, we propose a novel technique called Probabilistic Logic Minimization which relies on synthesizing an inexact circuit in the first place resulting in zero hardware overhead. Extensive simulations of the datapath elements designed using the proposed technique demonstrate that normalized gains as high as 2X-9.5X in the Energy-Delay-Area product can be obtained when compared to the corresponding correct designs, with a relative error magnitude percentage as low as 0.001% upto 1%.
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References
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Lingamneni, A., Enz, C., Palem, K., Piguet, C. (2011). Parsimonious Circuits for Error-Tolerant Applications through Probabilistic Logic Minimization . In: Ayala, J.L., García-Cámara, B., Prieto, M., Ruggiero, M., Sicard, G. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. PATMOS 2011. Lecture Notes in Computer Science, vol 6951. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-24154-3_21
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DOI: https://doi.org/10.1007/978-3-642-24154-3_21
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