Abstract
This paper presents SWAT, a highly optimised statistical timing analyser for digital circuits that combines transistor-level analysis accuracy with gate-level analysis performance. It is based upon a CSM for logic cells which considers transistor aging and process variation. Static timing analysis is performed using a very accurate waveform model. SWAT employs waveform truncation and dedicated solvers to significantly improve analysis performance without noticeable loss of accuracy. Parameter variations and aging can be handled both by Monte Carlo simulations and by a special sensitivity propagation mode, which expresses arrival times as a function of local and global parameter variations. Simulation times for ISCAS85 circuits are less then 2s for nominal and less than 28s for sensitivity mode.
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Knoth, C., Uphoff, C., Kiesel, S., Schlichtmann, U. (2011). SWAT: Simulator for Waveform-Accurate Timing Including Parameter Variations and Transistor Aging. In: Ayala, J.L., García-Cámara, B., Prieto, M., Ruggiero, M., Sicard, G. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. PATMOS 2011. Lecture Notes in Computer Science, vol 6951. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-24154-3_20
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DOI: https://doi.org/10.1007/978-3-642-24154-3_20
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-24153-6
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