The Study on RF Front-End Circuit Design Based on Low-Noise Amplifier Architecture

  • Zhao San-ping
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 236)


In this paper, a low power, high linearity and high gain front-end circuit with novel LNA in 0.18μm CMOS technology for 5.2 GHz wireless applications is proposed. By employing current-bleeding and current-enhanced techniques, the conversion gain and the linearity can be increased and the power consumption is reduced. The complementary common-gate LNA is adopted to reduce noise and to improve linearity. With the LO power of 0 dBm, the proposed front-end circuit has conversion gain of 18.4 dB, input 1-dB compression point of -16 dBm and IIP3 of -6 dBm, while it consumes only 9.4mW. The chip size including pads is 0.767mm × 0.96mm.


RF Front-end Circuit Low-noise Amplifier 


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Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Zhao San-ping
    • 1
  1. 1.Hebi Vocational and Technical CollegeChina

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