Abstract
As it is well known by electronic designers, each fabrication process has its own design rules and specific features. However, there are some alternatives usually provided by almost every standard foundry, presented and discussed in this chapter. Section 4.1 explains Variable Threshold CMOS devices and the use of multi-threshold transistors to reduce power consumption. The different body biasing alternatives are shown in Section 4.1. Gate length downscaling is a constant trend in modern CMOS processes, its impact being crucial in several key parameters of RF circuit performance. Therefore in Section 4.2 a discussion on the different cross-influences is presented. Finally, Chapter 4 closes with a discussion of the benefits of SOI processes.
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Alvarado, U., Bistué, G., Adín, I. (2011). Technology Structural Alternatives in Standard CMOS Technologies for Low-Power Analog Design. In: Low Power RF Circuit Design in Standard CMOS Technology. Lecture Notes in Electrical Engineering, vol 104. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-22987-9_4
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DOI: https://doi.org/10.1007/978-3-642-22987-9_4
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