Abstract
This paper presents an UML based tool for incompatible hardware Intellectual properties (IPs) integration. Our aim is to provide Systems On Chips (SOCs) designers with a UML based environment for modeling incompatible IPs, automatic generation of interface between IPs, and functional simulation. In our case, each IP is modeled as an UML component with a well defined interface including input and output signals and some attributes. The whole SOC is modeled via UML structure diagram. Memory timing constraints are modeled via UML timing diagrams. Communication protocols for incompatible IPs are modeled via UML Statecharts with hierarchic and concurrent states. From these diagrams, a Finite State Machine with Data path (FSMD) for interface is generated automatically. Functional simulation of the interface is performed by translating the result FSMD to a VHDL code.
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References
Jerraya, A.A., Wolf, W.: Multiprocessor systems on chip. Morgan Kaufmann publishers, San Francisco (2005)
Wagner, F.R., Cesario, W.O., Carro, L., Jerraya, A.A.: Strategies for integration of hardware and software IP components in embedded systems on chip. VLSI Journal (2004)
Borriello, G., Katz, R.: Synthesis and optimization of interface transducer logic. In: Proceedings of the International Conference on Computer-Aided Design, pp. 274–277 (November 1987)
Lin, B., Vercauteren, S.: Synthesis of concurrent system interface modules with automatic protocol conversion generation. In: Proceedings of the International Conference on Computer-Aided Design, pp. 101–108 (November 1994)
Narayan, S., Gajski, D.: Interfacing incompatible protocols using interface process generation. In: Proceedings of the Design Automation Conference, pp. 468–473 (June 1995 November 1994)
Passerone, R., Rowson, J.A., Sangiovanni-Vincentelli, A.: Automatic synthesis of interfaces between incompatible protocols. In: Proceedings of the Design Automation Conference, pp. 8–13 (June 1998)
Shin, D., Gajski, D.: Queue Generation Algorithm for Interface Synthesis. Technical Report ICS-TR-02-03, University of California, Irvine (February 2002)
Shin, D., Gajski, D.: Interface synthesis from protocol specification. Technical Report CECS-02-13, University of California, Irvine (April 12, 2002)
OCP-IP, http://www.ocp-ip.org
Booch, G., Rumbaugh, J., Jacobson, I.: Unified Modeling Language User Guide. Addison-Wesley, Reading (1999)
Schattkowsky, T.: UML2.0 Overview and Perspectives in SOC Design. In: Proceedings of the Design, Automation and Test in Europe (DATE 2005), vol. 2 (2005)
Gajski, D., Vahid, F., Narayan, S., Gong, J.: Specification and Design of Embedded Systems, p. 07632. Prentice Hall, Englewood (1994)
IEEE Standard VHDL Language Reference Manual. IEEE, IEEE Std 1076 (2000)
ModelSim documentation, ftp://ftp.xilinx.com/pub/documentation
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© 2011 Springer-Verlag Berlin Heidelberg
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Boutekkouk, F., Tolba, Z., Okab, M. (2011). Automatic Interface Generation between Incompatible Intellectual Properties (IPs) from UML Models. In: Abraham, A., Lloret Mauri, J., Buford, J.F., Suzuki, J., Thampi, S.M. (eds) Advances in Computing and Communications. ACC 2011. Communications in Computer and Information Science, vol 191. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-22714-1_5
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DOI: https://doi.org/10.1007/978-3-642-22714-1_5
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-22713-4
Online ISBN: 978-3-642-22714-1
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