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An FPGA-Based Fault-Tolerant 2D Systolic Array for Matrix Multiplications

  • Tadayoshi Horita
  • Itsuo Takanami
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6750)

Abstract

This paper proposes a method to implement fault-tolerant self-reconfigurable 2D systolic arrays to calculate matrix multiplications on FPGAs. The array uses a 1.5-track switching network for reconfiguration. The array implemented is compared to the corresponding non-redundant case by simulations of concrete examples, in terms of hardware size, total array reliability where not only faults of processing elements but also faults in the 1.5-track switching network are considered, computation time and electricity consumption. The simulation results show that the fault-tolerant array is better than the corresponding non-redundant one, in terms of the total array reliability, even if faults in the 1.5-track switching network are not negligible. In Appendix, we discuss the relation between the fault rates of the proposed fault-tolerant array and the corresponding non-redundant one and show that the former can be significantly decreased for the array of large size.

Keywords

systolic array 1.5-track switches FPGA run-time fault-tolerance self-reconfiguration 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Tadayoshi Horita
    • 1
    • 2
  • Itsuo Takanami
    • 1
    • 2
  1. 1.Department of Information and Computer SciencePolytecnic UniversityJapan
  2. 2.Ichinoseki national college of technology in former timesIwate-kenJapan

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