Implementation of Fault Secure Encoder and Decoder for Memory Application

Abstract

Memory cells have been protected from soft errors for more than a decade; due to the increase in soft error rate in logic circuits, the encoder and decoder circuitry around the memory blocks have become susceptible to soft errors as well and must also be protected. An attempt is made to implement the FPGA based fault-tolerant memory architecture whichtolerates transient faults both in the storageunit and in the supporting logic (i.e., encoder, corrector,and detector circuitries) by using the Euclidean Geometry Low-Density Parity-Check(EG-LDPC) code. This architecture is authorized in Verilog, behavior simulation using the ISE simulator and synthesis by using the synthesis Xilinx ISE 9.1. This is a new approach to design fault-secure encoder and decoder circuitry for memory designs and to identify and define a new class of error correcting codes whose redundancy makes the design of fault-secure detectors (FSD) particularly simple.