Abstract
This paper describes a novel model-order reduction (MOR) method to reduce the number of mutual inductances in conjunction with a recently proposed MOR algorithm, PartMOR. As the method produces passive mutual inductances as a reduction realization, it extends the existing RLC-in–RLC-out PartMOR to a RLCM-in–RLCM-out MOR method. The method is verified and compared to a well-known MOR method with test simulations and is shown to produce good reduction results in terms of CPU speed-up and generated error.
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References
Miettinen, P., Honkala, M., Roos, J., Valtonen, M.: PartMOR: Partitioning-based realizable model-order reduction method for RLC circuits. IEEE Trans. CAD, 30(3), 374–387 (2011)
Odabasioglu, A., Celik, M., Pileggi, L.T.: PRIMA: passive reduced-order interconnect macromodeling algorithm. IEEE Trans. CAD, 17, 645–654 (1998)
Freund, R.W.: SPRIM: structure-preserving reduced-order interconnect macromodeling, In: Proceedings of ICCAD’04, pp. 80–87. San Jose, California, Nov (2004)
Liao, H., Dai,W.W.-M.: Partitioning and reduction of RC interconnect networks based on scattering parameter macromodels. In: Proceedings of ICCAD’95, San Jose, California, pp. 704–709 (1995)
P. Miettinen, Honkala, M., Roos, J.: Partitioning-based RL-in–RL-out MOR method. In: Roos, J., Costa L.R.J. (eds.) Scientific Computing in Electrical Engineering SCEE 2008 Mathematics in Industry vol. 14, pp. 547–554. Springer, Berlin Heidelberg (2010)
Qin, Z., Cheng, C. K.: Realizable parasitic reduction using generalized Y-Δ transformation. In: Proceedings of DAC’03, pp. 220–225. Anaheim, Nov (2003)
Lin, T., Beattie, M.W., Pileggi, L.T: On the efficacy of simplified 2D on-chip inductance models. In: Proceedings of DAC’02, pp. 757–762. New Orleans, June (2002)
Yang, F., Zeng, X., Su, Y., Zhou, D.: RLCSYN: RLC equivalent circuit synthesis for structure-preserved reduced-order model of interconnect. In: Proceedings of ISCAS’07, New Orleans, pp. 2710–2713 (2007)
DeCarlo, R. A., Lin, P.-M.: Linear Circuit Analysis: Time Domain, Phasor, and Laplace Transformation Approaches. Oxford University Press, New York (2001)
Matsumoto, Y., Tanji, Y., Tanaka, M.: Efficient SPICE-netlist representation of reduced-order interconnect Model. In: Proceedings of ECCTD 2001, vol. 2, pp. 145–148 (2001)
Acknowledgements
This work was partially funded by the Graduate School in Electronics, Telecommunications and Automation (GETA). Financial support from the Nokia Foundation and the Foundation of Walter Ahlström is acknowledged.
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Miettinen, P., Honkala, M., Roos, J., Valtonen, M. (2012). Partitioning-Based Reduction of Circuits with Mutual Inductances. In: Michielsen, B., Poirier, JR. (eds) Scientific Computing in Electrical Engineering SCEE 2010. Mathematics in Industry(), vol 16. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-22453-9_42
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DOI: https://doi.org/10.1007/978-3-642-22453-9_42
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