Abstract
This paper describes a methodology for identifying custom instructions for critical code segments of embedded applications, considering the available data bandwidth constraint between custom logic and the base processor. Our approach enables designers to optionally constrain the number of input and output operands for custom instructions to reach the acceptable performance. We describe a design flow to establish the desired performance. We study the effects of input/output constraints and registerfile read/write ports on overall speedup of the system. Our experiments show that, in most cases, the solutions with the highest merit are not identified with relaxed input/output constraints. Results for packet-processing benchmarks covering cryptography, lookup, and classification show speed-up up to 40%.
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Yazdanbakhsh, A., Salehi, M.E. (2011). IO-Aware Custom Instruction Exploration for Customizing Embedded Processors. In: Park, J.J., Yang, L.T., Lee, C. (eds) Future Information Technology. Communications in Computer and Information Science, vol 184. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-22333-4_7
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DOI: https://doi.org/10.1007/978-3-642-22333-4_7
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