Page Coloring Synchronization for Improving Cache Performance in Virtualization Environment

  • Junghoon Kim
  • Jeehong Kim
  • Deukhyeon Ahn
  • Young Ik Eom
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6784)


The paging scheme randomly translates the virtual address into the physical address. Thus, it can lead to some serious problems like performance non-determinism and poor cache performance. In order to resolve these problems, page coloring is applied to operating systems such as Solaris, FreeBSD, and Windows. However, there is a problem applying page coloring in virtualization environment. The paging scheme translates the virtual address of the guest into the physical address of the guest which is not the real physical address. In this paper, we introduce a technique that can be used for synchronizing the page color between guest virtual machine (VM) and host machine. We name this technique page coloring synchronization. Our technique has some advantages such as reducing performance non-determinism and improving cache performance in virtualization environment. Our experiments demonstrate that if our technique is applied to the virtual machine monitor (VMM), it improves the performance up to 6.3%. Also, our experiments show that our technique can reduce performance non-determinism.


Page coloring Page coloring synchronization Cache performance Performance non-determinism Memory virtualization 


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  1. 1.
    Hwang, J., Suh, S., Heo, S., Park, C., Ryu, J., Park, S., Kim, C.: Xen on Arm: System Virtualization using Xen Hypervisor for ARM-based Secure Mobile Phones. In: 5th Annual IEEE Consumer Communications & Networking Conference, pp. 257–261 (2008)Google Scholar
  2. 2.
    McDougall, R., Anderson, J.: Virtualization Performance: Perspectives and Challenges Ahead. ACM SIGOPS Operating Systems Review 44(4), 40–56 (2010)CrossRefGoogle Scholar
  3. 3.
    Zhang, X., Dwarkadas, S., Shen, K.: Towards Practical Page Coloring-based Multi-core Cache Management. In: 4th ACM European Conference on Computer Systems (EuroSys), pp. 89–102 (2009)Google Scholar
  4. 4.
    Lynch, W., Bray, B., Flynn, M.: The Effect of Page Allocations on Caches. In: 25th Annual International Symposium on Microarchitecture, pp. 222–225 (1992)Google Scholar
  5. 5.
    Bershad, B., Lee, D., Romer, T., Chen, J.: Avoiding Conflict Misses Dynamically in Large Direct-Mapped Caches. In: 6th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pp. 158–170 (1994)Google Scholar
  6. 6.
    Sherwood, T., Calder, B., Emer, J.: Reducing Cache Misses Using Hardware and Software Page Placement. In: 13th International Conference on Supercomputing, pp. 155–164 (1999)Google Scholar
  7. 7.
    Cho, S., Jin, L.: Managing Distributed, Shared L2 Caches through OS-Level Page Allocation. In: 39th Annual International Symposium on Microarchitecture (2006)Google Scholar
  8. 8.
    Kessler, R., Hill, M.: Page Placement Algorithms for Large Real-Indexed Caches. ACM Transactions on Computer Systems 10(4), 338–359 (1992)CrossRefGoogle Scholar
  9. 9.
    Bugnion, E., Anderson, J., Lam, M.: Compiler-Directed Page Coloring for Multiprocessors. In: 7th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pp. 244–255 (1996)Google Scholar
  10. 10.
    Taylor, G., Davies, P., Farmwald, M.: The TLB Slice – A Low-Cost High-Speed Address Translation Mechanism. In: 17th International Symposium on Computer Architecture (ISCA), pp. 355–363 (1990)Google Scholar
  11. 11.
    Tam, D., Azimi, R., Soares, L., Stumm, M.: Managing Shared L2 Caches on Multicore Systems in Software. In: Workshop on the Interaction between Operating Systems and Computer Architecture (2007)Google Scholar
  12. 12.
    Soares, L., Tam, D., Stumm, M.: Reducing the Harmful Effects of Last-Level Cache Polluters with an OS-Level, Software-Only Pollute Buffer. In: 41th Annual International Symposium on Microarchitecture, pp. 258–269 (2008)Google Scholar
  13. 13.
    Lin, J., Lu, Q., Ding, X., Zhang, Z., Zhang, X., Sadayappan, P.: Gaining Insights into Multicore Cache Partitioning: Bridging the Gap between Simulation and Real Systems. In: International Symposium on High-Performance Computer Architecture (HPCA), pp. 367–378 (2008)Google Scholar
  14. 14.
    McDougall, R., Mauro, J.: Solaris Internals: Solaris 10 and OpenSolaris Kernel Architecture. Sun Microsystems Press (2006)Google Scholar
  15. 15.
    Dillon, M.: Design Elements of the FreeBSD VM System,
  16. 16.
    Russinovich, M., Solomon, D.: Microsoft Windows Internals. In: Microsoft Windows Server(TM) 2003, Windows XP, Windows 2000 (Pro-Developer), 4th edn., Microsoft Press, Redmond (2004)Google Scholar
  17. 17.
    Barham, P., Dragovic, B., Fraser, K., Hand, S., Harris, T., Ho, A., Neugebauer, R., Pratt, I., Warfield, A.: Xen and the Art of Virtualization. In: 19th ACM Symposium on Operating Systems Principles (SOSP), pp. 164–177 (2003)Google Scholar
  18. 18.
    Neiger, G., Santoni, A., Leung, F., Rodgers, D., Uhlig, R.: Intel Virtualization Technology: Hardware Support for Efficient Processor Virtualization. Intel Technology Journal 10(3) (2006)Google Scholar
  19. 19.
    Kernel Based Virtual Machine (KVM),
  20. 20.
    SysBench: A System Performance Benchmark,

Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Junghoon Kim
    • 1
  • Jeehong Kim
    • 1
  • Deukhyeon Ahn
    • 1
  • Young Ik Eom
    • 1
  1. 1.School of Information and Communication Eng.Sungkyunkwan UniversitySuwon, Gyeonggi-doKorea

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