Abstract
To reduce the power consumption and die area of interpolation filters, which usually determine the hardware cost of Delta-Sigma DAC systems, an improved common subexpression elimination (CSE) method is proposed in this paper. Furthermore, an improved comb filter with an optimized sharpening technique is put forward, which effectively provides sufficient sideband suppression and passband droop compensation. Using a TSMC 0.35μm Logic 1P4M process, the synthesis results show remarkable reduction in both power consumption and silicon area. Compared with several other FIR deign methods, the adder-cost is reduced significantly while the logic-depth is kept the same with the NR-SCSE, which is consistent with expectations.
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Wu, T., Wu, X., Zhao, M., Zhao, J. (2011). An Optimized Low-Power and Low-Complexity Interpolation Filter for Delta-Sigma DAC. In: Wan, X. (eds) Electrical Power Systems and Computers. Lecture Notes in Electrical Engineering, vol 99. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-21747-0_90
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DOI: https://doi.org/10.1007/978-3-642-21747-0_90
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-21746-3
Online ISBN: 978-3-642-21747-0
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