Advertisement

Design of an Improved Multiplier Unit for an Experimental RISC CPU

  • Ajay Joshi
  • Siew Lam
  • Yee Chan
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 99)

Abstract

An 8-bit RISC-CPU designed at gate level using completely custom based chip approach. CPU has an 8-bit integer unit and 16-bit floating point unit. The circuits are optimized by using more efficient algorithms. The algorithm discussed in this paper was applied for an efficient Multiplier design. An attempt has been made to improve conventional[6] algorithm. This paper discusses the design of an efficient Multiplier unit, with respect to its algorithm and VHDL implementation. The project was implemented using VHDL and simulated using Altera MaxPlus II simulation software which can map the design into Altera CPLD.

Keywords

Multiplier CPU simulation algorithm Floating point unit VHDL 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Akkas, A., Schulte, M.J.: Dual-mode floating-point multiplier architectures with parallel operations. Journal of Systems Architecture 52, 549–562 (2006)CrossRefGoogle Scholar
  2. 2.
    Joshi, A., Lam, S.L., Chan, Y.Y.: Algorithm & design of an efficient floating point ADD/SUB unit for an experimental CPU. International Journal of Intelligent Information Technology Application 2(6), 273–278 (2009)Google Scholar
  3. 3.
    Hamid, L.S.A., Shehata, K., El-Ghitani, H., ElSaid, M.: Design of Generic Floating Point Multiplier and Adder/Subtractor Units. In: 12th International on Conference Computer Modelling and Simulation (UKSim) 2010, Cambridge, pp. 615–618. Morgan Kaufmann, San Francisco (1999)Google Scholar
  4. 4.
    Stallings, W.: Computer Organization and Architecture, 6th edn. Pierson &Prentice-Hall, Englewood Cliffs (2003)Google Scholar
  5. 5.
    Even, G., Mueller, S.M., Seidel, P.M.: A dual precision IEEE floating-point multiplier. Integration, the VLSI Journal 29(2), 167–180 (2000), ISSN:0167-9260zbMATHCrossRefGoogle Scholar
  6. 6.
    Hida, Y., Li, X.S., Bailey, D.H.: Algorithms for Quad-Double Precision Floating Point Arithmetic. In: Proceedings of the 15th IEEE Symposium on Computer Arithmetic, p. 155 (2001)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Ajay Joshi
    • 1
  • Siew Lam
    • 2
  • Yee Chan
    • 2
  1. 1.Department of Electrical and Computer EnggThe University of the West IndiesSt. AugustineTrinidad and Tobago
  2. 2.Faculty of EngineeringMultimedia UniversityCyberjayaMalaysia

Personalised recommendations