Design of an Improved Multiplier Unit for an Experimental RISC CPU
An 8-bit RISC-CPU designed at gate level using completely custom based chip approach. CPU has an 8-bit integer unit and 16-bit floating point unit. The circuits are optimized by using more efficient algorithms. The algorithm discussed in this paper was applied for an efficient Multiplier design. An attempt has been made to improve conventional algorithm. This paper discusses the design of an efficient Multiplier unit, with respect to its algorithm and VHDL implementation. The project was implemented using VHDL and simulated using Altera MaxPlus II simulation software which can map the design into Altera CPLD.
KeywordsMultiplier CPU simulation algorithm Floating point unit VHDL
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