Abstract
This paper presents a chip implementation of fast frame synchronous scheme for forward error correction (FEC) layer of 10 Gb/s Ethernet frame. The fast frame synchronous methodology is achieved by changing the endian mode, the improved error trapper circuit can work in both syndrome generator mode and error trapper mode. One is the current syndrome generator; the other is the improved error trapper which works in syndrome generator mode. The two syndrome generators can work in parallel. When frame is synchronized, the error trapper can return to its normal working mode. A kind of network device that realizes the FEC functions is designed and a test network topology is set up to test and evaluate the FEC method. Experimental result shows that the frame synchronizing speed is twice that of the conventional method, while the hardware overhead is very small.
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Zhang, B., Zhang, L., Li, W., Zhu, C. (2011). A Fast Frame Synchronous Methodology Used in the Chip Implementation for 10Gb/s FEC-Coded Ethernet Frame. In: Wan, X. (eds) Electrical Power Systems and Computers. Lecture Notes in Electrical Engineering, vol 99. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-21747-0_14
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DOI: https://doi.org/10.1007/978-3-642-21747-0_14
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