Skip to main content

Evolutionary Algorithms in the Optimal Sizing of Analog Circuits

  • Chapter
Intelligent Computational Optimization in Engineering

Abstract

Analog signal processing applications such as filter design and oscillators, require the use of different kinds of amplifiers, namely: voltage follower, current conveyors, operational amplifiers and current feedback operational amplifiers. To improve the performances on these applications, it is very much needed to optimize the behavior of the amplifiers. That way, this work shows their optimization by applying two evolutionary algorithms: the Non-Sorting Genetic Algorithm (NSGA-II), and the Multiobjective Evolutionary Algorithm Based on Decomposition (MOEA/D). The analog circuits are sized taking into account design constraints, and linking HSPICE like circuit simulator to evaluate their electrical characteristics. Additionally, we show that differential evolution (DE) enhances the convergence to the Pareto front and controls the evolution of the objectives among different runs. DE also preserves the same time efficiency and increases the dominance on NSGA-II and MOEA/D compared with the one point crossover genetic operator.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Biolek, D., Senani, R., Biolkova, V., Kolka, Z.: Active elements for analog signal processing: Classification, review, and new proposals. Radioengineering 17(4), 15–32 (2008)

    Google Scholar 

  2. Tlelo-Cuautle, E., Duarte-Villaseñor, M.A., Guerra-Gómez, I.: Automatic synthesis of VFs and VMs by applying genetic algorithms. Circuits, Systems, Signal Processing 27(3), 391–403 (2008)

    Article  Google Scholar 

  3. Tlelo-Cuautle, E., Duarte-Villaseñor, M.A.: Evolutionary electronics: automatic synthesis of analog circuits by GAs. In: Yang Ang, B.L.T., Yin, S. (eds.) Success in Evolutionary Computation. SCI, pp. 165–188. IGI Global (2008)

    Google Scholar 

  4. Tlelo-Cuautle, E., Duarte-Villaseñor, M.A., Reyes-García, C.A., Reyes-Salgado, G.: Automatic synthesis of electronic circuits using genetic algorithms. Computación y Sistemas 10(3), 217–229 (2007)

    Google Scholar 

  5. Tlelo-Cuautle, E., Moro-Frías, D., Sánchez-López, C., Duarte-Villaseñor, M.A.: Synthesis of CCII-s by superimposing VFs and CFs through genetic operations. IEICE Electron. Express 5(11), 411–417 (2008)

    Article  Google Scholar 

  6. McConaghy, T., Gielen, G.G.E.: Template-Free Symbolic Performance Modeling of Analog Circuits via Canonical-Form Functions and Genetic Programming. IEEE Trans on Computer-Aided Design of integrated circuits 28(8), 1162–1175 (2009)

    Article  Google Scholar 

  7. Sánchez-López, C., Tlelo-Cuautle, E.: Symbolic Behavioral Model Generation of Current-Mode Analog Circuits. In: Proc. IEEE ISCAS, pp. 2761–2764 (2009)

    Google Scholar 

  8. Martens, E., Gielen, G.: ANTIGONE: Top-down creation of analog-to-digital converter architectures. Integration-The VLSI Journal 42(1), 10–23 (2009)

    Article  Google Scholar 

  9. Ramesh, C., Rusu, A., Ismail, M., Ismail, M., Skoglund, M.: System co-optimization in wireless receiver design with TrACS. Analog Integrated Circuits and Signal Processing 1-2, 117–127 (2008)

    Article  Google Scholar 

  10. Tlelo-Cuautle, E., Guerra-Gómez, I., Reyes-García, C.A., Duarte-Villaseñor, M.A.: Synthesis of Analog Circuits by Genetic Algorithms and their Optimization by Particle Swarm Optimization. In: Chiong, R. (ed.) Intelligent Systems for Automated Learning and Adaptation: Emerging Trends and Applications, pp. 173–192. IGI Global (2010), doi:10.4018/978-1-60566-798-0.ch008

    Google Scholar 

  11. McConaghy, T., Palmers, P., Steyaert, M., Gielen, G.: Variation-Aware Structural Synthesis of Analog Circuits via Hierarchical Building Blocks and Structural Homotopy. IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems 28(9), 1281–1294 (2009)

    Article  Google Scholar 

  12. Liu, B., Fernandez, F.V., Gielen, G., Castro-López, R., Roca, E.: A Memetic Approach to the Automatic Design of High-Performance Analog Integrated Circuits. ACM Trans on Design Automation of Electronic Systems 14(3), 1–24 (2009)

    MATH  Google Scholar 

  13. Gielen, G., Martens, E.: Classification of analog synthesis tools based on their architecture selection mechanisms. Integration, the VLSI Journal 41(2), 238–252 (2008)

    Article  Google Scholar 

  14. Rutenbar, R.A., Gielen, G., Roychowdhury, J.: Hierarchical modeling, optimization, and synthesis for system-level analog and RF designs. Proc. of the IEEE 95(3), 640–669 (2007)

    Article  Google Scholar 

  15. Fakhfakh, M., Masmoudi, S., Tlelo-Cuautle, E., Loulou, M.: Synthesis of switched current memory cells using the nullor approach and application to the design of high performance SI sigma delta modulators. WSEAS Trans. on Electronics, Special Issue: Modern circuit components for analogue signal processing and their applications 5(6), 265–273 (2008)

    Google Scholar 

  16. Gupta, S., Bhaskar, D., Senani, R.: New voltage controlled oscillators using CFOAs. AEU-Int. J. of Electronics and Communications 63(3), 209–217 (2009)

    Article  Google Scholar 

  17. Alzaher, H.: CMOS digitally programmable quadrature oscillators. Int. Journal of Circuit Theory and Applications 36(8), 953–966 (2008)

    Article  Google Scholar 

  18. Sánchez-López, C., Castro-Hernández, A., Perez-Trejo, A.: Experimental verification of the chua’s circuit designed with UGC. IEICE Electron. Express 5(17), 657–661 (2008)

    Article  Google Scholar 

  19. Sánchez-López, C., Trejo-Guerra, R., Muñoz-Pacheco, J.M., Tlelo-Cuautle, E.: N-scroll chaotic attractors from saturated functions employing CCII+s. Nonlinear Dynamics 61(1-2), 331–341 (2010), doi:10.1007/s11071-009-9652-3.

    Article  MATH  Google Scholar 

  20. Trejo-Guerra, R., Tlelo-Cuautle, E., Cruz-Hernández, C., Sánchez-López, C.: Chaotic communication system using Chua’s oscillators realized with CCII+s. Int. Journal of Bifurcations and Chaos 19(12), 4217–4226 (2009)

    Article  Google Scholar 

  21. Castro-López, R., Roca, E., Fernández, F.V.: Multimode pareto fronts for design of reconfigurable analogue circuits. Electronics Letters 45(2), 95–96 (2009)

    Article  Google Scholar 

  22. Liu, B., Wanga, Y., Yu, Z., Liu, L., Li, M., Wanga, Z., Lu, J., Fernández, F.V.: Analog circuit optimization system based on hybrid evolutionary algorithms. Integration, the VLSI Journal 42(2), 137–148 (2009)

    Article  Google Scholar 

  23. Fakhfakh, M.: A novel alienor-based heuristic for the optimal design of analog circuits. Microelectronics Journal 40, 141–148 (2009)

    Article  MathSciNet  Google Scholar 

  24. Guerra-Gómez, I., Tlelo-Cuautle, E., Li, P., Gielen, G.: Simulation-based optimization of UGCs performances. In: IEEE Int. Caribbean Conference on Devices, Circuits and Systems (2008)

    Google Scholar 

  25. Eeckelaert, T., McConaghy, T., Gielen, G.: Efficient multiobjective synthesis of analog circuits using hierarchical Pareto-optimal performance hypersurfaces. In: Proc. Design Automation and Test in Europe, vol. 2(1), pp. 1070–1075 (2005)

    Google Scholar 

  26. Fakhfakh, M., Cooren, Y., Sallem, A., Loulou, M., Siarry, P.: Analog Circuit Design Optimization through the Particle Swarm Optimization Technique. Analog Integrated Circuits and Signal Processing 63(1), 71–82 (2010), doi:10.1007/s10470-009-9361-3.

    Article  Google Scholar 

  27. Medeiro, F., Rodríguez-Macías, R., Fernández, F.V., Domínguez-Castro, R., Huertas, J.L., Rodríguez-Vázquez, A.: Global design of analog cells using statistical optimization techniques. Analog Integrated Circuits and Signal Processing 6, 179–195 (1994)

    Article  Google Scholar 

  28. Barros, M., Guilherme, J., Horta, N.: Analog circuits optimization based on evolutionary computation techniques in Integration. The VLSI Journal 43(1), 136–155 (2010)

    Article  Google Scholar 

  29. Deb, K., Pratap, A., Agarwal, S., Meyarivan, T.: A fast and elitist multiobjective genetic algorithm: NSGA-II. IEEE Trans. Evolutionary Computation 6(2), 182–197 (2002)

    Article  Google Scholar 

  30. Zitzler, E., Deb, K., Thiele, L.: Comparison of multiobjective evolutionary algorithms: Empirical results. IEEE Trans. Evolutionary Computation 8(2), 173–195 (2000)

    Google Scholar 

  31. Li, H., Zhang, Q.: Multiobjective optimization problems with complicated pareto sets, MOEA/D and NSGA-II. IEEE Trans. Evolutionary Computation 13(2), 284–302 (2009)

    Article  Google Scholar 

  32. Olensek, J., Burmen, A., Puhan, J., Tuma, T.: DESA: a new hybrid global optimization method and its application to analog integrated circuit sizing. Journal of Global Optimization 44(1), 53–77 (2008)

    Article  MathSciNet  Google Scholar 

  33. Guerra-Gómez, I., Tlelo-Cuautle, E., Reyes-García, C.A., Reyes-Salgado, G., de la Fraga, L.G.: Non-sorting genetic algorithm in the optimization of unity-gain cells. In: 6th International Conference on Electrical and Electronics Engineering, Toluca, Mexico, November 11-13, pp. 364–367. IEEE Press, Los Alamitos (2009)

    Google Scholar 

  34. Guerra-Gómez, I., Tlelo-Cuautle, E., McConaghy, T., Gielen, G.: Optimizing current conveyors by evolutionary algorithms including differential evolution. In: IEEE ICECS Special Session: Applications of Evolutionary Computation Techniques to Analog, Mixed-Signal and RF Circuit Design, Hammamet, Tunisia, December 13-16, pp. 259–262 (2009)

    Google Scholar 

  35. Roca, I., Fakhfakh, M., Castro-López, R., Fernández, F.V.: Applications of Evolutionary Computation Techniques to Analog, Mixed-Signal and RF Circuit Design An Overview. In: IEEE ICECS Special Session: Applications of Evolutionary Computation Techniques to Analog, Mixed-Signal and RF Circuit Design, Hammamet, Tunisia, December 13-16, pp. 251–254 (2009)

    Google Scholar 

  36. Guerra-Gómez, I., Tlelo-Cuautle, E., McConaghy, T., Gielen, G.: Decomposition-Based Multi-Objective Optimization of Second Generation Current Conveyors. In: IEEE MWSCAS, pp. 220–223 (2009)

    Google Scholar 

  37. Polanco-Martagón, S., Flores-Becerra, G., Tlelo-Cuautle, E.: Computing Optimum Sizes of a Voltage Follower using Fuzzy Sets. In: Tlelo-Cuautle, E., Polanco-Martagón, S. (eds.) IEEE MWSCAS, Applying Fuzzy Sets Intersection in the Sizing of Voltage Followers, LANMR, vol. 533, pp.209–216, 216–219 (2009), http://CEUR-WS.org/Vol-533/

  38. Polanco-Martagón, S., Flores-Becerra, G., Tlelo-Cuautle, E.: Fuzzy Set Based Approach to Compute Optimum Sizes of Voltage Followers. In: IEEE ICECS, Hammamet, Tunisia, December 13-16, pp. 844–847 (2009)

    Google Scholar 

  39. Maricau, E., De Wit, P., Gielen, G.: An analytical model for hot carrier degradation in nanoscale CMOS suitable for the simulation of degradation in analog IC applications. Microelectronics Reliability 48(8-9), 1576–1580 (2008)

    Article  Google Scholar 

  40. McConaghy, T., Gielen, G.G.E.: Globally Reliable Variation-Aware Sizing of Analog Integrated Circuits via Response Surfaces and Structural Homotopy. IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems 28(11), 1627–1640 (2009)

    Article  Google Scholar 

  41. Torres-Muñoz, D., Tlelo-Cuautle, E.: Automatic biasing and sizing of CMOS analog integrated circuits. In: IEEE MWSCAS, pp. 915–918 (2005)

    Google Scholar 

  42. Storn, R., Price, K.: Minimizing the real functions of the ICEC’96 contest by Differential Evolution. In: IEEE International Conference on Evolutionary Computation, pp. 842–844 (1996)

    Google Scholar 

  43. Storn, R.: Diferential Evolution Research – Trends and Open Questions in Advances in Differential Evolution. Springer, Heidelberg (2008)

    Google Scholar 

  44. Zhang, J., Sanderson, A.C.: JADE: Self-Adaptive Differential Evolution with Fast and Reliable Convergence Performance. In: 2007 IEEE Congress on Evolutionary Computation, pp. 2251–2258 (2007)

    Google Scholar 

  45. Iorio, A.W., Li, X.: Solving rotated multi-objective optimization problems using differential evolution. In: Webb, G.I., Yu, X. (eds.) AI 2004. LNCS (LNAI), vol. 3339, pp. 861–872. Springer, Heidelberg (2004)

    Chapter  Google Scholar 

  46. Zhang, Q., Hui, L.: MOEA/D: A Multiobjective Evolutionary Algorithm Based on Decomposition. IEEE Transactions on Evolutionary Computation 11(6), 712–731 (2007)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2011 Springer-Verlag Berlin Heidelberg

About this chapter

Cite this chapter

Tlelo-Cuautle, E. et al. (2011). Evolutionary Algorithms in the Optimal Sizing of Analog Circuits. In: Köppen, M., Schaefer, G., Abraham, A. (eds) Intelligent Computational Optimization in Engineering. Studies in Computational Intelligence, vol 366. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-21705-0_5

Download citation

  • DOI: https://doi.org/10.1007/978-3-642-21705-0_5

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-21704-3

  • Online ISBN: 978-3-642-21705-0

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics