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OpenMP Extensions for Heterogeneous Architectures

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OpenMP in the Petascale Era (IWOMP 2011)

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 6665))

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Abstract

Modern architectures are becoming more heterogeneous. OpenMP currently has no mechanism for assigning work to specific parts of these heterogeneous architectures. We propose a combination of thread mapping and subteams as a means to give programmers control over how work is allocated on these architectures. Experiments with a prototype implementation on the Cell Broadband Engine show the benefit of allowing OpenMP teams to be created across the different elements of a heterogeneous architecture.

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References

  1. Ayguade, E., Badia, R.M., Cabrera, D., Duran, A., Gonzalez, M., Igual, F., Jimenez, D., Labarta, J., Martorell, X., Mayo, R., Perez, J.M., Quintana-Ortí, E.S.: A proposal to extend the openMP tasking model for heterogeneous architectures. In: Müller, M.S., de Supinski, B.R., Chapman, B.M. (eds.) IWOMP 2009. LNCS, vol. 5568, pp. 154–167. Springer, Heidelberg (2009)

    Chapter  Google Scholar 

  2. Chen, T., Raghavan, R., Dale, J.N., Iwata, E.: Cell broadband engine architecture and its first implementation; a performance view. IBM Journal of Research and Development 51(5), 559 (2007)

    Article  Google Scholar 

  3. Chen, T., Sura, Z., O’Brien, K., O’Brien, J.K.: Optimizing the use of static buffers for DMA on a CELL chip. In: Almási, G.S., Caşcaval, C., Wu, P. (eds.) KSEM 2006. LNCS, vol. 4382, pp. 314–329. Springer, Heidelberg (2007)

    Chapter  Google Scholar 

  4. Chen, T., Zhang, T., Sura, Z., Tallada, M.G.: Prefetching irregular references for software cache on cell. In: Proceedings of the Sixth Annual IEEE/ACM International Symposium on Code Generation and Optimization, p. 155 (2008)

    Google Scholar 

  5. Dolbeau, R., Bihan, S., Bodin, F.: Hmpp: A hybrid multi-core parallel programming environment. In: First Workshop on General Purpose Processing on Graphics Processing Units (2007)

    Google Scholar 

  6. Ferrer, R., Beltran, V., Gonzàlez, M., Martorell, X., Ayguadé, E.: Analysis of task offloading for accelerators. In: Patt, Y.N., Foglia, P., Duesterwald, E., Faraboschi, P., Martorell, X. (eds.) HiPEAC 2010. LNCS, vol. 5952, pp. 322–336. Springer, Heidelberg (2010)

    Chapter  Google Scholar 

  7. Gonzàlez, M., O’Brien, K., Vujic, N., Martorell, X., Ayguadé, E., Eichenberger, A.E., Chen, T., Sura, Z., Zhang, T., O’Brien, K.: Hybrid access-specific software cache techniques for the cell be architecture. In: Proceedings of the 17th international conference on Parallel architectures and compilation techniques - PACT 2008. p. 292 (2008)

    Google Scholar 

  8. Huang, L., Chapman, B., Liao, C.: An implementation and evaluation of thread subteam for openmp extensions. In: Workshop on Programming Models for Ubiquitous Parallelism (PMUP 2006), Seattle, WA (2006)

    Google Scholar 

  9. Jin, H., Frumkin, M., Yan, J.: The openmp implementation of nas parallel benchmarks and its performance. Tech. rep. (1999), http://www.nas.nasa.gov/News/Techreports/1999/PDF/nas-99-011.pdf

  10. OpenMP Architecture Review Board: Openmp application program interface. Tech. rep. (2008), http://www.openmp.org/mp-documents/spec30.pdf

  11. Wolfe, M.: Implementing the pgi accelerator model. In: GPGPU 2010: Proceedings of the 3rd Workshop on GPGPUs, pp. 43–50. ACM, New York (2010)

    Google Scholar 

  12. Wong, M., Klemm, M., Duran, A., Mattson, T., Haab, G., de Supinski, B.R., Churbanov, A.: Towards an error model for openMP. In: Sato, M., Hanawa, T., Müller, M.S., Chapman, B.M., de Supinski, B.R. (eds.) IWOMP 2010. LNCS, vol. 6132, pp. 70–82. Springer, Heidelberg (2010)

    Chapter  Google Scholar 

  13. Zhang, G.: Extending the openMP standard for thread mapping and grouping. In: Mueller, M.S., Chapman, B.M., de Supinski, B.R., Malony, A.D., Voss, M. (eds.) IWOMP 2005 and IWOMP 2006. LNCS, vol. 4315, pp. 435–446. Springer, Heidelberg (2008)

    Chapter  Google Scholar 

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White, L. (2011). OpenMP Extensions for Heterogeneous Architectures. In: Chapman, B.M., Gropp, W.D., Kumaran, K., Müller, M.S. (eds) OpenMP in the Petascale Era. IWOMP 2011. Lecture Notes in Computer Science, vol 6665. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-21487-5_8

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  • DOI: https://doi.org/10.1007/978-3-642-21487-5_8

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-21486-8

  • Online ISBN: 978-3-642-21487-5

  • eBook Packages: Computer ScienceComputer Science (R0)

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