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Interpreter Instruction Scheduling

  • Stefan Brunthaler
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6601)

Abstract

Whenever we extend the instruction set of an interpreter, we risk increased instruction cache miss penalties. We can alleviate this problem by selecting instructions from the instruction set and re-arranging them such that frequent instruction sequences are co-located in memory. We take these frequent instruction sequences from hot program traces of external programs and we report a maximum speedup by a factor of 1.142. Thus, interpreter instruction scheduling complements the improved efficiency of an extended instruction set by optimizing its instruction arrangement.

Keywords

Virtual Machine Instruction Schedule Open List Instruction Cache Benchmark Program 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Stefan Brunthaler
    • 1
  1. 1.Institut für ComputersprachenTechnische Universität WienWienAustria

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