Abstract
Whenever we extend the instruction set of an interpreter, we risk increased instruction cache miss penalties. We can alleviate this problem by selecting instructions from the instruction set and re-arranging them such that frequent instruction sequences are co-located in memory. We take these frequent instruction sequences from hot program traces of external programs and we report a maximum speedup by a factor of 1.142. Thus, interpreter instruction scheduling complements the improved efficiency of an extended instruction set by optimizing its instruction arrangement.
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References
Open Research Compiler (October 2010), http://ipf-orc.sourceforge.net/
Bell, J.R.: Threaded code. Communications of the ACM 16(6), 370–372 (1973)
Brunthaler, S.: Efficient interpretation using quickening. In: Proceedings of the 6th Symposium on Dynamic Languages (DLS 2010), Reno, Nevada, US, October 18, ACM Press, New York (2010)
Brunthaler, S.: Inline caching meets quickening. In: D’Hondt, T. (ed.) ECOOP 2010. LNCS, vol. 6183, pp. 429–451. Springer, Heidelberg (2010)
Ertl, M.A., Gregg, D.: Optimizing indirect branch prediction accuracy in virtual machine interpreters. In: Proceedings of the SIGPLAN 2003 Conference on Programming Language Design and Implementation (PLDI 2003), pp. 278–288. ACM, New York (2003)
Fulgham, B.: The computer language benchmarks game, http://shootout.alioth.debian.org/
Intel: Intel Turbo Boost Technology in Intel Core microarchitecture (Nehalem) based processors. Online (November 2008), http://download.intel.com/design/processor/applnots/320354.pdf?iid=tech_tb+paper
Lin, C.-C., Chen, C.-L.: Code arrangement of embedded java virtual machine for NAND flash memory. In: Stenström, P., Dubois, M., Katevenis, M., Gupta, R., Ungerer, T. (eds.) HiPEAC 2007. LNCS, vol. 4917, pp. 369–383. Springer, Heidelberg (2008)
Pettis, K., Hansen, R.C.: Profile guided code positioning. SIGPLAN Notices 25(6), 16–27 (1990)
Ramírez, A., Larriba-Pey, J.L., Navarro, C., Torrellas, J., Valero, M.: Software trace cache. In: Proceedings of the 13th International Conference on Supercomputing (ICS 1999), Rhodes, Greece, June 20-25, pp. 119–126. ACM, New York (1999)
Zhao, P., Amaral, J.N.: Feedback-directed switch-case statement optimization. In: Proceedings of the International Conference on Parallel Programming Workshops (ICPP 2005 Workshops), Oslo, Norway, June 14-17, pp. 295–302. IEEE, Los Alamitos (2005)
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Brunthaler, S. (2011). Interpreter Instruction Scheduling. In: Knoop, J. (eds) Compiler Construction. CC 2011. Lecture Notes in Computer Science, vol 6601. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-19861-8_10
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DOI: https://doi.org/10.1007/978-3-642-19861-8_10
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-19860-1
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