Abstract
Voltage scaling is the most effective solution in building energy efficient digital circuits. Reduction of the supply voltage (with a fixed threshold voltage) results in a quadratic reduction of dynamic energy at the expense of decreased performance. In this work, we investigate performances of CPAL (Complementary Pass-transistor Adiabatic Logic) circuits operating in near-threshold and super-threshold regions. The impacts on both energy efficiency and robustness are also discussed. Compressor 4:2 circuits using standard static CMOS, medium-voltage static CMOS, standard CPAL and medium-voltage CPAL are verified. The results show that the energy consumption of the medium-voltage CPAL circuits is greatly reduced with high robustness and reasonable speed.
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Hu, J., Liu, B. (2011). Energy Efficient Medium-Voltage Circuits Based on Adiabatic CPL. In: Qi, L. (eds) Information and Automation. ISIA 2010. Communications in Computer and Information Science, vol 86. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-19853-3_80
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DOI: https://doi.org/10.1007/978-3-642-19853-3_80
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-19852-6
Online ISBN: 978-3-642-19853-3
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