Design of CMOS Wilkinson Power Divider Incorporating Semi-passive Inductors

Abstract

In this paper, a Wilkinson power divider incorporating semi-passive inductors is designed in a standard 0.18-μm CMOS process. The lumped power divider is based on series-C and shunt-L networks, and the shunt inductors utilize a center-tapped inductor feedback technique to achieve high-Q factors. Compared with conventional transformer feedback architectures, this proposed technique not only compensates resistive losses with low-power consumption but also achieves high-Q factors. The lumped power divider is designed at a center frequency of 5.0 GHz for equal power dividing with all ports matched to 50 Ω. The circuit consumes a total power of 2.5 mW from a 0.8-V supply voltage, and the isolation between the output ports is about 28 dB. Moreover, the insertion, input, and output return losses of the circuits at 5 GHz are 0.02 dB, 30 dB, and 35 dB, respectively.