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Optimal Test Time and Power for System-On-Chip Designs Using Game Theory

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Future Intelligent Information Systems

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 86))

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Abstract

This paper proposes a nonzero two-person no-cooperative game theory model for core based SoC test scheduling to minimize test application time and test power. The existence of Nash equilibration has been proved. Nash equilibration gives the Pareto solution of the problem. Experimental results prove that the proposed method achieves better results than the existing methods.

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References

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© 2011 Springer-Verlag Berlin Heidelberg

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Shao, J., Lun, L., Liu, M., Li, Y., Zhang, R. (2011). Optimal Test Time and Power for System-On-Chip Designs Using Game Theory. In: Zeng, D. (eds) Future Intelligent Information Systems. Lecture Notes in Electrical Engineering, vol 86. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-19706-2_11

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  • DOI: https://doi.org/10.1007/978-3-642-19706-2_11

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-19705-5

  • Online ISBN: 978-3-642-19706-2

  • eBook Packages: EngineeringEngineering (R0)

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