Abstract
In this chapter, current status of environmental radiation-induced failures in SRAM is introduced. Alpha ray-induced soft-error has been a major concern for soft-errors in memories until late 1980s. Threat from environmental neutron-induced soft-error is growing with a rapid pace from early 1990s as device scaling proceeds. General features in charge collection mode soft-errors are reviewed and analyzed based on simulation results from the Monte Carlo soft-error simulator CORIMS. Combining with conventional charge collection mechanisms causing soft-error in SRAMs, new bipolar error mechanisms are confirmed under high-energy neutron-accelerated tests. The error mode is initially referred as “battery effect” and then referred as multi-coupled bipolar interaction (MCBI), based on theoretical/simulation studies with 2- or 4-bit 3D SRAM models. Countermeasure combining error correction code (ECC) and interleave turned out to be robust against this novel error mode.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
E.L. Petersen, The SEU figure of merit and proton upset rate calculations IEEE Trans. Nucl. Sci. 45(6), 2550–2562 (1998)
P.E. Dodd et al., Impact of ion energy on single-event upset. IEEE Trans. Nucl. Sci 45(6), 2483–2491 (1998)
T. Goka, H. Matsumoto, N. Nemoto, SEE flight data from Japanese satellites. IEEE Trans. Nucl. Sci. 45(6), 2771–2778 (1998)
R. Koga, Single event sensitivities of 128- and 256-megabit synchronous dynamic random access memories (SDRAMs), in Proceedings of the 4th International Workshop on Radiation Effects on Semiconductor Devices for Space Application, Tsukuba, 15–18 May 2000, pp. 81–88
E. Normand Extensions of burst generation rate method for wider application to proton/neutron-induced single event effects. IEEE Trans. Nucl. Sci 45(6), 2904–2914 (1998)
E. Normand, T.J. Baker, Altitude and latitude variations in avionics SEU and atmospheric neutron flux IEEE Trans. Nucl. Sci. 40(6), 1484–1490 (1993)
T. Nakamura, Y. Uwamino, T. Ohkubo, A. Hara, Altitude variation of cosmic-ray neutrons. Health Phys. 53(5), 509–517 (1987)
T.C. May, M.H. Woods, Alpha-particle-induced soft errors in dynamic memories. IEEE Trans. Electron Devices ED-26(1), 2–9 (1979)
J.F. Ziegler, W.A. Lanford, Effect of cosmic rays on computer memories. Science 206(4420), 776–788 (1979)
E. Takeda, K. Takeuchi, E. Yamazaki, T. Toyabe, K. Ohshima, K. Itoh, Effective funneling length in alpha-particle induced soft errors in Extended Abstracts of the 18th Conference on Solid State Devices and Materials, Tokyo, pp. 311–314 (1986)
A. Eto, M. Hidaka, Y. Okuyama, K. Kimura, M. Hosono, impact of neutron flux on soft errors in MOS memories, International Electron Devices Meeting, San Francisco, CA, December 6–9, pp. 367–370 (1998)
D.C. Bossen, CMOS soft errors and server design, in Workshop on Radiation Induced Soft Errors in Silicon Components and Computer Systems, IRPS, Dallas, 7 April 2002
C. Slayman, Eliminating the threat of soft errors – a system vendor perspective, in IRPS Panel Discussion on Eliminating the Threat of Soft Errors, Dallas, 2 April 2003, No. 6
E. Normand, Single event upset at ground level. IEEE Trans. Nucl. Sci. 43(6), 2742–2750 (1996)
E. Ibe, Current and future trend on cosmic-ray-neutron induced single event upset at the ground down to 0.1-micron-device, in TSL Workshop on Applied Physics, Uppsala, 3 May 2001, No. 1
E. Ibe, Y. Yahagi, F. Kataoka, Y. Saito, A. Eto, M. Sato, H. Kameyama, M. Hidaka, A self-consistent integrated system for terrestrial-neutron induced single event upset of semiconductor devices at the ground, in 2002 ICITA, Buthurst, No. 273–21 (2002)
T. Nakamura, M. Baba, E. Ibe, Y. Yahagi, H. Kameyama, Terrestrial Neutron-Induced Soft-Errors in Advanced Memory Devices (World Scientific, New Jersey, 2008)
L. Borucki, G. Schindlbeck, C. Slayman, Comparison of accelerated DRAM soft error rates measured at component and system level, in IRPS 2008, Phoenix Convention Center, Phoenix, 27 April – 1 May 2008 No. 5A.4
G. Gasiot, D. Giot, P. Roche, alpha-induced multiple cell upsets in standard and radiation hardened SRAMs manufactured in a 65 nm CMOS technology (TNS). Trans. Nucl. Sci 53(6), 3479–3486 (2006)
P. Shivakumar, M. Kistler, S.W. Keckler, D. Burger, A. Lorenzo, Modeling the effect of technology trends on the soft error rate of combinational logic, in International Conference on Dependable Systems and Networks, pp. 389–398 (2002)
N. Seifert, X. Zhu, L. Massengill, Impact of scaling on soft-error rates in commercial microprocessors. Trans. Nucl. Sci. 49(6), 3100–3106 (2002)
S. Mitra, M. Zhang, S. Waqas, N. Seifert, B. Gill, K.S. Kim, Combinational logic soft error correction, in The Second Workshop on System Effects of Logic Soft Errors, Urbana-Champain, 11–12 April 2006
S. Hareland et al., Impact of CMOS process scaling and SOI on the soft error rates of logic processes, in Symposium on VLSI Technology Digest of Technical Papers, pp. 73–74 (2001)
M. Baze, J. Wert, J. Clement, M. Hubert, A. Witulski, Propagating SET characterization technique for digital CMOS libraries, in International Nuclear and Space Radiation Effects Conference, Ponte Vedra Beach, 17–21 July 2006, No. E4
N. Seifert, B. Gill, M. Zhang, V. Zia, V. Ambrose, On the scalability of redundancy based SER mitigation schemes, in ICICDT2007, Austin, 18–20 May 2007, No. G2, pp. 197–205
P.E. Dodd, M.R. Shaneyfelt, D.S. Walsh, J.R. Schwank, G.L. Hash, R.A. Loemker, B.L. Draper P.S. Winokur, Single-event upset and snapback in silicon-on-insulator devices and integrated circuits. Trans. Nucl. Sci. 47(6), 2165–2174 (2000)
Schwank, J.R., Dodd, P.E., Felix, J.A., Sexton, F.W., Hash, G.L., M.R. Shaneyfelt, J. Baggio, V. Ferlet-Cavrois, P. Paillet, E. Blackmore, Effects of particle energy on proton and neutron-induced single-event latchup, in 2005 IEEE Nuclear and Space Radiation Effects Conference, Seattle, 11–15 July 2005, No. I-4
P.E. Dodd, M.R. Shaneyfelt, J.R. Schwank, G.L. Hash, Neutron-induced softerrors, latchup, and comparison of SER test methods for SRAM technologies, in IEDM, No. 13.2 (2002)
R. Koga, S. Penzin, K. Crawford, W. Crain, Single event functional interrupt (SEFI) sensitivity in microcircuits in Proceedings of RADECS 1997, pp. 311–318 (1997)
Actel, Understanding soft and firm errors in semiconductor devices (2003), www.actel.com
S Huang, G.A.J. Amaratunga, Analysis of SEB and SEGR in super-junction MOSFETs. Trans. Nucl. Sci. 47(6) 2640–2647 (2000)
S. Kuboyama, K. Sugimoto, S. Shugyo, S. Matsuda, T. Hirao, Single-event burnout of epitaxial bipolar transistors. Trans. Nucl. Sci 45(6), 2527–2533 (1998)
E. Normand, J.L. Wert, D.L. Oberg, P.P. Majewski, P. Voss, SA Wender, Neutron-induced single event burnout in high voltage electronics. Trans. Nucl. Sci 44, 2358–2368 (1997)
Semiconductor Industry Association, Technology Node Challenges, International Technology Roadmap for Semiconductors, 1999 Edition (1999)
Y. Yahagi, E. Ibe, S. Yamamoto, Y. Yoshino, M. Sato, Y. Takahashi, H. Kameyama, A. Saito, M. Hidaka, Versatility of SEU function and its derivation from the irradiation tests with well-defined white neutron beams. Trans. Nucl. Sci 52(5), 1562–1567 (2005)
Y. Yahagi, E. Ibe, Y. Saito, A. Eto, M. Sato, “Self-Consistent Integrated System for Susceptibility to Terrestrial-Neutron Induced Soft-error of Sub-quarter Micron Memory Devices, 2002 IRW (Stanford Sierra Camp, South Lake Tahoe, 2002), pp. 143–146
Y. Yahagi, E. Ibe, Y. Takahashi, Y. Saito, A. Eto, M. Sato, H. Kameyama, M. Hidaka, K. Terunuma, T. Nunomiya, T. Nakamura, Threshold energy of neutron-induced single event upset as a critical factor, in 2004 IEEE International Reliability Physics Symposium, Phoenix, 25–29 April 2004, pp. 669–670
JESD89A, Measurement and reporting of alpha particles and terrestrial cosmic ray-induced soft errors in semiconductor devices, Revision of JEDEC Standard No. 89, October 2006
J. Maiz, S. Hareland, K. Zhang, P. Armstrong, Characterization of multi-bit soft error events in advanced SRAMs, in Technical Digest of IEEE International Electron Device Meeting (IEDM) 2003, Washington, 7–10 December 2003, No. 21.4
D. Giot, G. Gasiot, P. Roche, Multiple bit upset analysis in 90 nm SRAMs, in 9th European Workshop on Radiation Effects on Components and Systems, Athens, 27–29 September 2006, No.A-7, pp. 26–29
R. Baumann, The impact of technology scaling on soft error rate performance and limits to the efficacy of error correction, in Inter. Electron Devices Meeting (IEDM) Tech. Digest, San Francisco, 8–11 December 2002, pp. 329–332
T.C. May, M.H. Woods, A new physical mechanism for soft errors in dynamic memories, in 16th Annual Proceedings of 1978 International Reliability Symposium, 18–20 April, San Diego, 1979, pp. 33–40
T.C. May, M.H. Woods, Alpha-particle-induced soft errors in dynamic memories. IEEE Trans. Electron Devices ED-26(1), 2–9 (1979)
D.S. Yaney, J.T. Nelson, L.L. Vanskike, Alpha-particle tracks in silicon and their effect on dynamic MOS RAM reliability. IEEE Trans. Electron Devices ED-26(1), 10–16 (1979)
M. Koyanagi, H. Sunami, N. Hashimoto, M. Ishikawa, Novel high density, stacked capacitor MOS RAM, in Inter. Electron Devices Meeting (IEDM) Tech. Digest, Washington, 4–6 December 1978, pp. 348–351
H. Sunami, T. Kume, N. Hashimoto, K. Ito, T. Toyabe, S. Asai, A corrugated capacitor cell (CCC) for megabit dynamic MOS memories, in Inter. Electron Devices Meeting (IEDM) Tech. Digest, San Francisco, 13–15 December 1982, pp. 806–809
H. Shinnriki, T. Kisu, S. Kimura, Y. Nishioka, Y. Kawamoto, K. Mukai, Promising storage capacitor structures with thin Ta2O5 film low-power high-density DRAM’s. IEEE Trans. Electron Devices 37(9), 1939–1947 (1990)
Y. Nishioka, H. Shinriki, K. Mukai, Influence of SiO2 at the Ta2O5/Si interface on dielectric characteristics of Ta2O5 capacitors. J. Appl. Phys. 61(6), 2335–2338 (1987)
S. Takehiro, S. Yamauchi, M. Yoshimaru, H. Onoda, The simple stacked BST capacitor for the future DRAMs using a novel low temperature growth enhanced crystallization, in Digest of 1997 Symposium on VLSI Technology, Kyoto, June 10–12, pp. 153–154 (1997)
Y. Kohyama, T. Ozaki, S. Yoshida, Y. Ishibashi, H. Nitta, S. Inoue, K. Nakamura, T. Aoyama, K. Imai, H. Hayasaka, A fully printable, self-aligned and planarized stacked capacitor DRAM cell technology for 1 Gbit DRAM and beyond, in Digest. of 1997 Symposium on VLSI Technology, Kyoto, June 10–12, pp. 17–18, (1997)
Y. Tosaka, K. Suzuki, S. Satoh, T. Sugii, Theoretical study of alpha-particle-induced soft errors in submicron SOI SRAM. IEICE Trans. Electron. E79-C(6), 767–771 (1996)
Y. Tosaka, S. Satoh, T. Itakura, K. Suzuki, T. Sugii, H. Ehara, G.A. Woffinden, Cosmic ray neutron-induced soft errors in sub-half micron CMOS circuits. IEEE Electron Device Lett. 18(3), 99–101 (1997)
Y. Tosaka, S. Satoh, T. Itakura, H. Ehara, T. Ueda, G.A. Woffinden, S.A. Wender, Measurement and analysis of neutron-induced soft errors in sub-half micron CMOS circuits. IEEE Trans. Electron Devices 45(7), 1453–1458 (1998)
Y. Hirano, T. Iwamura, K. Shiga, K. Nii, K. Sonoda, T. Matsumoto, S. Maeda, Y. Yamaguchi, T. Ipposhi, S. Maegawa, Y. Inoue, High soft-error tolerance body-tied SOI technology with partial trench isolation (PTI) for next generation devices, in 2002 Symposium on VLSI Technology: Digest of Technical Papers, 11–13 June, Honolulu, IEEE CAT. No. 01CH37303, JSAP CAT. No. AP021201, pp. 48–49, (2002)
H. Masuda, T. Toyabe, H. Shukuri, K. Ohshima, K. Itoh, A full three-dimensional simulation on alpha-particle induced DRAM soft errors, in Technical Digest – International Electron Devices Meeting, pp. 496–499 (1985)
C.M. Hsieh, P.C. Murley, R.R. O’Brien, A field-funneling effect on the collection of alpha-particle-generated carriers in silicon devices. IEEE Electron Device Lett. EDL-2(4), 103–105 (1981)
P.M. Carter, B.R. Wilkins, Influences on soft error rates in static RAM’s. IEEE J. Solid-State Circuits SC-22(3), 430–436 (1987)
S. Satoh, R. Sudo, H. Tashiro, N. Higaki, N. Nakayama, CMOS-SRAM soft-error simulation system, in 1994 IEEE/IPRS, p. 339
K. Takeuchi, K. Shimohigashi, E. Takeda, E. Yamasaki, T. Toyabe, K. Itoh, Alpha-particle-induced charge collection measurements for megabit DRAM cells. IEEE Trans. Electron Devices ED-36(9), 1644–1650 (1989)
K. Takeuchi, K. Shimohigashi, H. Kozuka, T. Toyabe, K. Itoh, H. Kurosawa, Origin and characteristics of alpha-particle-induced permanent junction leakage. IEEE Trans. Electron Devices ED-37(3), 730–736 (1990)
E. Takeda, K. Takeuchi, E. Yamasaki, T. Toyabe, K. Ohshima, K. Itoh, The scaling law of alpha-particle induced soft errors for VLSI’s, in IEDM ‘86, pp. 542–545 (1986)
H. Shin, Modeling of alpha-particle-induced soft error rate in DRAM. IEEE Trans. Electron Devices 46(9), 1850–1857 (1999)
M. Minami, Y. Wakui, H. Matsuki, T. Nagano, A new soft-error-immune static memory cell having a vertical diver MOSFET with a buried source for ground potential. IEEE Trans. Electron Devices 36(9), 1657–1662 (1989)
K. Yamaguchi, Y. Takemura, K. Osada, K. Ishibashi, Y. Saito, Three-dimensional device modeling for SRAM soft-error immunity and tolerance analysis. IEEE Trans. Electron Devices 51(3), 378–388 (2004)
D. Leroy, R. Gaillard, E. Schaefer, C. Beltrando, S.-J. Wen, R. Wong, Variation of alpha induced soft error rate with technology node, in IOLTS 2008, Greece, 6–9 July 2008, No.11.2, pp. 253–260
E.P. Rech, S. Gerardin, A. Paccagnella, P. Bernardi, M. Grosso, M. Sonza Reorda, D. Appello, Evaluating alpha-induced soft errors in embedded microprocessors, in IOLTS2009, Sesimbra-Lisbon, 24–26 June 2009, No. 4.1, pp. 69–74
E. Ibe, Y. Yahagi, H. Kameyama, Y. Takahashi, Single event effects of semiconductor devices at the ground. Ionizing Radiation 30(7), 263–281, (2004)
M.S. Gordon, P. Goldhagen, K.P. Rodbell, T.H. Zabel, H.H.K. Tang, J.M. Clem, P. Bailey, Measurement of the flux and energy spectrum of cosmic-ray induced neutrons on the ground. IEEE Trans. Nucl. Sci. 51, 3427–3434 (2004)
C. Hu, Alpha-particle-induced field and enhanced collection of carriers. IEEE Electron Device Lett EDL-3(2), 31–34 (1982)
M. Baba, M. Takada, T. Iwasaki, S. Matsuyama, T. Nakamura et al, Development of monoenergetic neutron calibration fields between 8 keV and 15 MeV. Nucl. Instrum. Methods Phys. Res. A 376, 115–123 (1996)
M. Baba, H. Okamura, M. Hagiwara, T. Itoga, S. Kamada, Y. Yahagi, E. Ibe, Installation and application of an intense 7Li(p, n) neutron source for 20–90 MeV region. Radiat. Prot. Dosimetry 126(1–4), 13–17 (2007)
M. Baba, Installation and application of an intense 7Li(p, n) neutron source for 20–90 MeV region, in NEUDOS-10, Uppsala, 12–16 June 2006, No. A1–3
A.V. Prokofiev, O. Bystrom, C. Ekstrom, D. Reistad, D. Wessman, S. Pomp, J. Blomgren, M. Osterlund, U. Tippawan, V. Ziemann, A new neutron beam facility for SEE testing, in 2005 RADECS, Sep.19–23, Palais des Congres, Cap d’Agde, 2005, No.W-14
E. Ibe, Y. Yahagi, H. Yamaguchi, H. Kameyama, SEALER: novel Monte-Carlo simulator for single event effects of composite-materials semiconductor devices, in 2005 RADECS, Sep. 19–23, Palais des Congres, Cap d’Agde, 2005, No. E-4
T. Nakamura, T. Ninomiya, N. Hirabayashi, H. Suzuki, Y. Sato, Sequential measurements of energy spectrum and intensity for cosmic ray neutrons, in Proceedings of the 7th International Symposium on Natural Radiation Environment (NRE-VII), Rhodes, 20–24 May 2002
H.W. Bertini, A.H. Culkowski, O.W. Hermann, N.B. Gove, M.P. Guthrie, High energy(E ≦ 100 GeV) intranuclear cascade model for nucleons and pions incident on nuclei and comparisons with experimental data. Phys. Rev. C 17(4) 1382–1394 (1978)
I. Dostrovsky, Z. Fraenkel, G. Friedlander, Monte Carlo calculations of nuclear evaporation process. III. Applications to low-energy reactions. Phys. Rev. 116(3), 683–702 (1959)
F. Bertland, R. Peele, Complete hydrogen and helium particle spectra from 30- to 60-MeV proton bombardment of nuclei with A = 12 to 209 and comparison with the intranuclear cascade model. Phys. Rev. C Nucl. Phys. 8(3), 1045–1064 (1973)
H.H.K. Tang, G.R. Srinivasan, N. Azziz, Cascade statistical model for nucleon-induced reactions on light nuclei in the energy range 50-MeV-1 GeV. Phys. Rev. C 42(4), 1598–1622 (1990)
S. Satoh, Y. Tosaka, T. Itakura, Scaling law for secondary cosmic-ray neutron-induced soft errors in DRAMs, in Extended Abstracts of the 1998 ISDM, Hiroshima, pp. 40–41 (1998)
R.C. Baumann, E.B. Smith, Neutron-induced boron fission as a major source of soft errors in deep submicron SRAM devices, in 2000 IRPS, San Jose, 10–13 April 2000, pp. 152–157
E. Ibe, H. Taniguchi, Y. Yahagi, K. Shimbo, T. Toba, Impact of scaling on neutron-induced soft error in SRAMs from a 250 nm to a 22 nm design rule. Trans. Electron Device 57(7), 1527–1538, (2010)
J. Yamada, Selector-line merged built-in ECC technique for DRAM’s. IEEE J. Solid-State Circuits 22(5), 868–873 (1987)
K. Furutani, K. Arimoto, H. Miyamoto, T. Kobayashi, K. Yasuda, K. Mashiko, A built-in hamming code ECC circuit for DRAM’s. IEEE J. Solid-State Circuits 24(1), 50–56 (1989)
E. Ibe, S. Chung, S. Wen, Y. Yahagi, H. Kameyama, S. Yamamoto, T. Akioka, H. Yamaguchi, Valid and prompt track-down algorithms for multiple error mechanisms in neutron-induced single event effects of memory devices, in RADECS, Athens, 27–29 September 2006, No. D-2
E. Ibe, H. Kameyama, Y. Yahagi, K. Nishimoto, Y. Takahashi, Distinctive asymmetry in neutron-induced multiple error patterns of 0. 13 μm process SRAM, in The 6th International Workshop on Radiation Effects on Semiconductor Devices for Space Application, Tsukuba, 6–8 October 2004, pp. 19–23
E. Ibe, S. Chung, S. Wen, H. Yamaguchi, Y. Yahagi, H. Kameyama, S. Yamamoto, T. Akioka, Spreading diversity in multi-cell neutron-induced upsets with device scaling, in 2006 CICC, San Jose, 10–13 September 2006, pp. 437–444
E. Ibe, S.S. Chung, S.J. Wen, H. Yamaguchi, Y. Yahagi, H. Kameyama, S. Yamamoto, Multi-error propagation mechanisms clarified in CMOSFET SRAM devices under quasi-mono energetic neutron irradiation, in NSREC2006, Ponte Vedra Beach, No. PC-6 (2006)
K. Osada, J.L. Shin, M. Khan, Y. Liou, K. Wang, K. Shoji, K. Kuroda, S. Ikeda, K. Ishibashi, Universal-Vdd 0.65–2.0 V 32 kB cache using voltage-adapted timing-generation scheme and a lithographical-symmetric cell, in Proceedings of the IEEE International Solid-State Circuits Conference, February 2001, pp. 168–169
K. Osada, J.L. Shin, M. Khan, Y. Liou, K. Wang, K. Shoji, K. Kuroda, S. Ikeda, K. Ishibashi, Universal-Vdd 0.65–2.0-V 32-kB cache using voltage-adapted timing-generation scheme and a lithographical-symmetric cell. IEEE J. Solid-State Circuits 36(11), 1738–1744 (2001)
T. Toyabe, H. Masuda, Y. Aoki, H. Shukuri, T. Hagiwara, Three-dimensional device simulator CADDETH with highly convergent matrix solution algorithms. IEEE Trans. Electron Device 32(10), 2038–2044 (1985)
S.M. Sze, KK. Ng, Physics of Semiconductor Devices, 3rd edn. (Wiley Interscience, San Jose, 2006), pp. 7–133
S.M. Sze, KK. Ng, Physics of Semiconductor Devices, 3rd edn. (Wiley Interscience, San Jose, 2006), pp. 249–250
C. Lombardi, S. Manzini, A. Saporito, M. Vanzi, A physically based mobility model for numerical simulation of nonplanar devices. IEEE Trans. CAD 7, 1164–1171 (1988)
M. Valdinoci, D. Ventura, M.C. Vecchi, M. Rudan, G. Baccarani, F. Illien, A. Stricker, L. Zullino, Impact-ionization in silicon at large operating temperature, in International Conference on Simulation of Semiconductor Processes and Devices, September 1999
H. Yamaguchi, E. Ibe, Y. Yahagi, S. Yamamoto, T. Akioka, H. Kameyama, Novel mechanism of neutron-induced multi-cell error in CMOS devices tracked down from 3D device simulation, in Proceedings of the 2006 International Conference on Simulaton of Semiconductor Process and Devices (SISPAD), Monterey, 6–8 September 2006, pp. 184–187
K. Osada, K Yamaguchi, Y. Saitoh, T. Kawahara, Cosmic-ray multi-error immunity for SRAM, based on analysis of the parasitic bipolar effect, in Symposium on VLSI Circuits Digest, June 2003, pp. 255–256
K. Osada, Y. Saitoh, E. Ibe, K. Ishibashi, 16.7-fA/cell tunnel-leakage-suppressed 16-Mbit SRAM for handling cosmic-ray-induced multi-errors IEEE J. Solid-State Circuits 38(11), 1952–1957 (2003)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2011 Springer-Verlag Berlin Heidelberg
About this chapter
Cite this chapter
Ibe, E., Osada, K. (2011). Reliable Memory Cell Design for Environmental Radiation-Induced Failures in SRAM. In: Ishibashi, K., Osada, K. (eds) Low Power and Reliable SRAM Memory Cell and Array Design. Springer Series in Advanced Microelectronics, vol 31. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-19568-6_6
Download citation
DOI: https://doi.org/10.1007/978-3-642-19568-6_6
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-19567-9
Online ISBN: 978-3-642-19568-6
eBook Packages: EngineeringEngineering (R0)