Abstract
This chapter introduces fundamentals of SRAM memory cell. The basic SRAM cell design and the operation are also described in this chapter. In Sect.2.1, the most common SRAM cell, the full CMOS 6-T memory cell, is explained. In Sect.2.2, read and write basic operations are introduced. In Sect.2.3, the basic of electrical stability at read operation (static noise margin, SNM) is described.
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Reference
E. Seevinck, F.J. List, J. Lohstroh, Static-noise margin analysis of MOS SRAM cells. IEEE J. Solid-State Circuits SC-22(5), 748–754 (1987)
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© 2011 Springer-Verlag Berlin Heidelberg
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Osada, K. (2011). Fundamentals of SRAM Memory Cell. In: Ishibashi, K., Osada, K. (eds) Low Power and Reliable SRAM Memory Cell and Array Design. Springer Series in Advanced Microelectronics, vol 31. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-19568-6_2
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DOI: https://doi.org/10.1007/978-3-642-19568-6_2
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Online ISBN: 978-3-642-19568-6
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