Design of High Resolution, Fast Locking, Low Power Multiphase-Output Delay Locked Loop
This paper presents a fast locking, multiphase-output Delay Locked Loop(DLL). We propose a novel method to reduce locking time using a circuit which determines the input frequency thereby enabling the DLL to start output clock closest to reference clock(ref_clk). The DLL is designed in TSMC 0.18um technology. It has a frequency range from 105 MHz to 183 MHz with worst case resolution less than 350 ps. The DC power consumption of the DLL is approx. 2.8 mW at 1.8 V.
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