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Design of High Resolution, Fast Locking, Low Power Multiphase-Output Delay Locked Loop

  • Anu Gupta
  • Nirmalya Sanyal
  • Suman Kumar Panda
  • Satish Sankaralingam
  • Deepak Kumar Gupta
Part of the Communications in Computer and Information Science book series (CCIS, volume 142)

Abstract

This paper presents a fast locking, multiphase-output Delay Locked Loop(DLL). We propose a novel method to reduce locking time using a circuit which determines the input frequency thereby enabling the DLL to start output clock closest to reference clock(ref_clk). The DLL is designed in TSMC 0.18um technology. It has a frequency range from 105 MHz to 183 MHz with worst case resolution less than 350 ps. The DC power consumption of the DLL is approx. 2.8 mW at 1.8 V.

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References

  1. 1.
    Huang, P.-J., Chen, H.-M., Chang, R.C.: A novel start-controlled phase/frequency detector for multiphase-output delay-locked loops. In: Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, August 4-5, pp. 68–71 (2004), doi:10.1109/APASIC.2004.1349408Google Scholar
  2. 2.
    Cheng, J.: A delay-locked loop for multiple clock phases/delays generation, 005, 94 pages. Georgia Institute of Technology, 3198555Google Scholar
  3. 3.
    Booth, E.R.: Wide range, low jitter delay-locked loop using a graduated digital delay line and phase interpolator (November 2006)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Anu Gupta
    • 1
  • Nirmalya Sanyal
    • 1
  • Suman Kumar Panda
    • 1
  • Satish Sankaralingam
    • 1
  • Deepak Kumar Gupta
    • 1
  1. 1.Birla Institute of Technology and SciencePilaniIndia

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