Abstract
The power reduction is the crucial part in hardware architecture especially in the case of battery driven applications. In this paper, a low power and low area Lapped Biorthogonal Transform (LBT) for Field Programmable Gate Arrays (FPGAs) has been proposed based on flow graph algorithm (FGA) which significantly reduces the power and area. The proposed LBT is implemented in Cylcone III Nios II embedded evaluation kit using Quartus II tool. The simulation and synthesis result reveals that the proposed LBT significantly exhibits an improved performance. Hence it is suitable for low power, low area and high speed applications.
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© 2011 Springer-Verlag Berlin Heidelberg
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Deepa, P., Vasanthanayaki, C. (2011). Low Power Lapped Bi-orthogonal Transform (LBT) for FPGA’s. In: Das, V.V., Stephen, J., Chaba, Y. (eds) Computer Networks and Information Technologies. CNC 2011. Communications in Computer and Information Science, vol 142. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-19542-6_28
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DOI: https://doi.org/10.1007/978-3-642-19542-6_28
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-19541-9
Online ISBN: 978-3-642-19542-6
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