Design of Efficient Reversible Parallel Binary Adder/Subtractor

  • H. G. Rangaraju
  • U. Venugopal
  • K. N. Muralidhara
  • K. B. Raja
Part of the Communications in Computer and Information Science book series (CCIS, volume 142)


In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing etc. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible 8-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three design approaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractor in the existing design. The performance analysis is verified using number gates, Garbage inputs/outputs and Quantum Cost. It is observed that Reversible 8-bit Parallel Binary Adder/Subtractor with Design III is efficient compared to Design I and II.

Index Terms

Reversible Logic Garbage Input/output Quantum Cost Reversible Parallel Binary Adder/Subtractor 


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Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • H. G. Rangaraju
    • 1
  • U. Venugopal
    • 2
  • K. N. Muralidhara
    • 3
  • K. B. Raja
    • 2
  1. 1.Department of Electronics and Communication EngineeringGovernment Engineering CollegeChamarajanagarIndia
  2. 2.Department of Electronics and Communication EngineeringUniversity Visvesvaraya College of EngineeringBangaloreIndia
  3. 3.Department of Electronics and Communication EngineeringP E S College of EngineeringMandyaIndia

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