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Design of Efficient Reversible Parallel Binary Adder/Subtractor

  • H. G. Rangaraju
  • U. Venugopal
  • K. N. Muralidhara
  • K. B. Raja
Part of the Communications in Computer and Information Science book series (CCIS, volume 142)

Abstract

In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing etc. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible 8-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three design approaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractor in the existing design. The performance analysis is verified using number gates, Garbage inputs/outputs and Quantum Cost. It is observed that Reversible 8-bit Parallel Binary Adder/Subtractor with Design III is efficient compared to Design I and II.

Index Terms

Reversible Logic Garbage Input/output Quantum Cost Reversible Parallel Binary Adder/Subtractor 

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References

  1. 1.
    Landauer, R.: Irreversibility and Heat Generation in the Computational Process. IBM Journal of Research and Development 5(3), 183–191 (1961)MathSciNetCrossRefzbMATHGoogle Scholar
  2. 2.
    Bennett, C.H.: Logical Reversibility of Computation. IBM Journal of Research and Development 17(6), 525–532 (1973)MathSciNetCrossRefzbMATHGoogle Scholar
  3. 3.
    Mohammadi, M., Eshghi, M., Haghprast, M., Bahrololoom, A.: Design and Optimization of Reversible BCD Adder/Subtractor Circuit for Quantum and Nanotechnology Based Systems. Journal of Word Applied Science, 787–792 (2008)Google Scholar
  4. 4.
    Hung, W.N.N., Song, X., Yang, G., Yang, J., Perkowski, M.: Optimal Synthesis of Multiple Output Boolean Functions using a Set of Quantum Gates by Symbolic Reachability Analysis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25(9), 1652–1663 (2006)CrossRefGoogle Scholar
  5. 5.
    Thapliyal, H., Srinivas, M.B., Arabnia, H.R.: Reversible Logic Synthesis of Half, Full and Parallel Subtractors. In: Proceedings of the International Conference on Embedded Systems and Applications, pp. 165–181 (2005)Google Scholar
  6. 6.
    Thapliyal, H., Srinivas, M.B.: A New Reversible TSG gate and its Application for Designing Efficient Adder Circuits. In: International Symposium on Representations and Methodology of Future Computing Technologies (2005)Google Scholar
  7. 7.
    Islam, S., Islam, R.: Minimization of Reversible Adder Circuits. Asian Journal of Information Technology 4(12), 1146–1151 (2005)Google Scholar
  8. 8.
    Babu, H.M.H., Islam, M.R., Chowdhury, S.M.A., Chowdhury, A.R.: Synthesis of Full Adder Circuit using Reversible Logic. In: International Conference on VLSI Design, pp. 757–760 (2004)Google Scholar
  9. 9.
    Bruce, J.W., Thornton, M.A., Shivakumaraiah, L., Kokate, P.S., Li, X.: Efficient Adder Circuits Based on a Conservative Reversible Logic Gate. In: Proceedings of the IEEE Computer Society Annual Symposium on VLSI, pp. 83–88 (2002)Google Scholar
  10. 10.
    Thapliyal, H., Ranganathan, N.: Design of Efficient Reversible Binary Subtractors Based on a New Reversible Gate. In: Proceedings of the IEEE Computer Society Annual Symposium on VLSI, pp. 229–234 (2009)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • H. G. Rangaraju
    • 1
  • U. Venugopal
    • 2
  • K. N. Muralidhara
    • 3
  • K. B. Raja
    • 2
  1. 1.Department of Electronics and Communication EngineeringGovernment Engineering CollegeChamarajanagarIndia
  2. 2.Department of Electronics and Communication EngineeringUniversity Visvesvaraya College of EngineeringBangaloreIndia
  3. 3.Department of Electronics and Communication EngineeringP E S College of EngineeringMandyaIndia

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