Abstract
In this paper, we present a fast ICAP controller providing high-speed configuration and easy-to-use readback capabilities, reducing configuration overhead as much as possible. In order to enhance performance, FaRM uses techniques such as DMA, ICAP overclocking, bitstream pre-load into controller and bitstream compression, using an evolution of the Run Length Encoding algorithm. We also propose a reconfiguration overhead estimation model which gives a good idea of the overhead. This approach is tested with an AES encryption/decryption architecture. With proper ICAP overclocking to 200 MHz, we are able to reach the ICAP upper bound throughput of 800 MB/s.
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Duhem, F., Muller, F., Lorenzini, P. (2011). FaRM: Fast Reconfiguration Manager for Reducing Reconfiguration Time Overhead on FPGA. In: Koch, A., Krishnamurthy, R., McAllister, J., Woods, R., El-Ghazawi, T. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2011. Lecture Notes in Computer Science, vol 6578. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-19475-7_26
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DOI: https://doi.org/10.1007/978-3-642-19475-7_26
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-19474-0
Online ISBN: 978-3-642-19475-7
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