Abstract
The Cell processor is a typical example of a heterogeneous multiprocessor on-chip architecture that uses several levels of parallelism to deliver high performance. Reducing the gap between peak performance and effective performance is the challenge for software tool developers and the application developers. Image processing and media applications are typical “main stream” applications. We use the Harris algorithm for the detection of interest points in an image as a benchmark to compare the performance of several parallel schemes on a Cell processor. The impact of the DMA controlled data transfers and the synchronizations between SPEs explains the differences between the performance of the different parallelization schemes. The scalability of the architecture is modeled and evaluated.
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Saidani, T., Lacassagne, L., Falcou, J., Tadonki, C., Bouaziz, S. (2011). Parallelization Schemes for Memory Optimization on the Cell Processor: A Case Study on the Harris Corner Detector. In: Stenström, P. (eds) Transactions on High-Performance Embedded Architectures and Compilers III. Lecture Notes in Computer Science, vol 6590. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-19448-1_10
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DOI: https://doi.org/10.1007/978-3-642-19448-1_10
Publisher Name: Springer, Berlin, Heidelberg
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