Cost Effective High-Voltage IC Technology Implemented in a Standard CMOS Process

Abstract

For competitive high-voltage (HV) integrated circuit (IC) products an excellent trade-off between specific on-resistance R_on,sp and breakdown voltage BV of a HV lateral DMOS (LDMOS) transistor, while keeping low fabrication cost, is mandatory. This paper presents a review of the HVIC technology trend with special emphasis on cost effective 0.35 μm and 0.18 μm HV-CMOS technologies. Through optimized process setup and device engineering a very competitive R_on,sp-BV trade-off of a HV LDMOS transistor without degrading the low-voltage (LV) CMOS performance has been achieved. A 0.35μm HV-CMOS technology with LDMOS transistor operating voltages from 20V to 120V is reported. Only two mask level adders on top of standard CMOS are required to provide the full set of 3.3V, 5V and 20V-120V HV devices. This is the result of taking advantage of predictive TCAD which enables early optimization of device layouts and dopant concentrations. In addition, HV and LV process integration issues of a 0.18 μm HV-CMOS technology, which play a key role to efficiently implement a HV module into a deep submicron CMOS process, are described. Key issues of p-channel LDMOS transistors are reviewed. The hot-carrier (HC) behaviour of a 50 V p-channel LDMOS transistor is presented too.