Advertisement

An Efficient Low Power Multiple-Value Look-Up Table Targeting Quaternary FPGAs

  • Cristiano Lazzari
  • Jorge Fernandes
  • Paulo Flores
  • José Monteiro
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6448)

Abstract

FPGA structures are widely used as they enable early time-to-market and reduced non-recurring engineering costs in comparison to ASIC designs. Interconnections play a crucial role in modern FPGAs, because they dominate delay, power and area. Multiple-valued logic allows the reduction of the number of interconnections in the circuit, hence can serve as a mean to effectively curtail the impact of interconnections. In this work we propose a new look-up table structure based on a low-power high-speed quaternary voltage-mode device. The most important characteristics of the proposed architecture are that it is a voltage-mode structure, which allows reduced power consumption, and it is implemented with a standard CMOS technology. Our quaternary implementation overcomes previous proposed techniques with simple and efficient CMOS structures. Moreover, results show significant reductions on power consumption and timing in comparison to binary implementations with similar functionality.

Keywords

Multiple-value Logic Quaternary Logic Look-up Tables FPGAs Standard CMOS Technology 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Gupta, A.K., Dally, W.J.: Topology optimization of interconnection networks. IEEE Comput. Archit. Lett. 5(1), 3 (2006)CrossRefGoogle Scholar
  2. 2.
    Banerjee, K., Souri, S.J., Kapur, P., Saraswat, K.C.: 3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration. Proceedings of the IEEE 89(5), 602–633 (2001)CrossRefGoogle Scholar
  3. 3.
    Li, F., Lin, Y., He, L., Chen, D., Cong, J.: Power modeling and characteristics of field programmable gate arrays. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24(11), 1712–1724 (2005)CrossRefGoogle Scholar
  4. 4.
    Singh, A., Marek-Sadowska, M.: Efficient circuit clustering for area and power reduction in FPGAs. In: Proceedings of the 2002 ACM/SIGDA Tenth International Symposium on Field-Programmable Gate Arrays, FPGA 2002, pp. 59–66. ACM, New York (2002)CrossRefGoogle Scholar
  5. 5.
    da Silva, R., Lazzari, C., Boudinov, H., Carro, L.: CMOS voltage-mode quaternary look-up tables for multi-valued FPGAs. Microelectronics Journal 40(10), 1466–1470 (2009)CrossRefGoogle Scholar
  6. 6.
    Dubrova, E.: Multiple-valued logic in vlsi: Challenges and opportunities. In: Proceedings of NORCHIP 1999, pp. 340–350 (1999)Google Scholar
  7. 7.
    Gonzalez, A., Mazumder, P.: Multiple-valued signed digit adder using negative differential resistance devices. IEEE Transactions on Computers 47(9), 947–959 (1998)CrossRefGoogle Scholar
  8. 8.
    Hanyu, T., Kameyama, M.: A 200 MHz pipelined multiplier using 1.5 v-supply multiple-valued mos current-mode circuits with dual-rail source-coupled logic. IEEE Journal of Solid-State Circuits 30(11), 1239–1245 (1995)CrossRefGoogle Scholar
  9. 9.
    Zilic, Z., Vranesic, Z.: Multiple-valued logic in FPGAs. In: Proceedings of the 36th Midwest Symposium on Circuits and Systems, vol. 2, pp. 1553–1556 (August 1993)Google Scholar
  10. 10.
    Cunha, R., Boudinov, H., Carro, L.: Quaternary look-up tables using voltage-mode CMOS logic design. In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, pp. 56–56 (May 2007)Google Scholar
  11. 11.
    Cadence Design Systems Inc.: Virtuoso spectre simulator user guide (2010)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Cristiano Lazzari
    • 1
  • Jorge Fernandes
    • 2
  • Paulo Flores
    • 2
  • José Monteiro
    • 2
  1. 1.INESC-IDLisbonPortugal
  2. 2.INESC-ID / IST, TU LisbonLisbonPortugal

Personalised recommendations