Abstract
The performance of the sequential digital circuit (Speed, Power consumption etc.) depends upon the performance of flip-flop used in the design. ASIC design flows use characterized data of flip-flops for final signoff. Therefore it’s critical to know precisely the accuracy of characterized data with respect to the actual behavior of flip-flops on silicon. An on-chip flip-flop characterization circuit (FCC) has been presented here which gives the accurate estimation of various parameters of flip-flop such as CP-Q Delay, Setup time, Hold time and Power consumption. The system consists of a digital controller and characterization circuit which are based upon configurable oscillator which could be programmed to oscillate in different configurations or could be operated in functional mode for functional verification. The delay values are calculated by processing the value of time period of oscillator in different modes. The system was fabricated in 40nm CMOS technology and the flip-flop parameters are extracted from it.
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© 2011 Springer-Verlag Berlin Heidelberg
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Jain, A., Veggetti, A., Crippa, D., Rolandi, P. (2011). An On-Chip Flip-Flop Characterization Circuit. In: van Leuken, R., Sicard, G. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. PATMOS 2010. Lecture Notes in Computer Science, vol 6448. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-17752-1_5
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DOI: https://doi.org/10.1007/978-3-642-17752-1_5
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-17751-4
Online ISBN: 978-3-642-17752-1
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